Lines Matching +full:0 +full:x60005000
47 reg = < 0x00000000 0x40000000 >; /* 1GB RAM at 0x0 */
51 SOC: tegra20@0 {
56 bus-frequency = <0>;
61 #address-cells = <0>;
63 reg = < 0x50041000 0x1000 >, /* Distributor Registers */
64 < 0x50040100 0x0100 >; /* CPU Interface Registers */
70 #size-cells = <0>;
71 reg = < 0x50040200 0x100 >, /* Global Timer Registers */
72 < 0x50040600 0x100 >; /* Private Timer Registers */
79 reg = <0x60005000 0x8>;
86 reg = <0x60005008 0x8>;
93 reg = <0x60005010 0x8>;
98 reg = <0x60005050 0x8>;
105 reg = <0x60005058 0x8>;
112 reg = <0x70006000 0x40>;
121 reg = <0x70006040 0x40>;
130 reg = <0x70006200 0x100>;