Lines Matching +full:0 +full:x53fac000
44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0x0>;
52 d-cache-size = <0x8000>;
53 i-cache-size = <0x8000>;
55 l2-cache-line = <0x40000>;
56 timebase-frequency = <0>;
57 bus-frequency = <0>;
58 clock-frequency = <0>;
62 localbus@0fffc000 {
70 tzic: tz-interrupt-controller@0fffc000 {
74 reg = <0x0fffc000 0x00004000>;
87 * 0FFFC000 0FFFCFFF 0x4000 TZIC
106 /* 53FD4000 0x4000 CCM */
109 /* 63F80000 0x4000 DPLLIP1 */
110 /* 63F84000 0x4000 DPLLIP2 */
111 /* 63F88000 0x4000 DPLLIP3 */
112 reg = <0x53fd4000 0x4000
113 0x63F80000 0x4000
114 0x63F84000 0x4000
115 0x63F88000 0x4000>;
125 /* 53F84000 0x4000 GPIO1 */
128 reg = <0x53f84000 0x4000>;
138 /* 53F88000 0x4000 GPIO2 */
141 reg = <0x53f88000 0x4000>;
150 /* 53F8C000 0x4000 GPIO3 */
153 reg = <0x53f8c000 0x4000>;
162 /* 53F90000 0x4000 GPIO4 */
165 reg = <0x53f90000 0x4000>;
174 /* 53FDC000 0x4000 GPIO5 */
177 reg = <0x53fdc000 0x4000>;
186 /* 53FE0000 0x4000 GPIO6 */
189 reg = <0x53fe0000 0x4000>;
198 /* 53FE4000 0x4000 GPIO5 */
201 reg = <0x53fe4000 0x4000>;
217 /* 50004000 0x4000 ESDHC 1 */
220 reg = <0x50004000 0x4000>;
225 /* 50008000 0x4000 ESDHC 2 */
228 reg = <0x50008000 0x4000>;
233 /* 5000C000 0x4000 UART 3 */
236 reg = <0x5000c000 0x4000>;
242 /* 50010000 0x4000 eCSPI1 */
245 #size-cells = <0>;
247 reg = <0x50010000 0x4000>;
253 /* 50014000 0x4000 SSI2 irq30 */
256 reg = <0x50014000 0x4000>;
262 /* 50020000 0x4000 ESDHC 3 */
265 reg = <0x50020000 0x4000>;
271 /* 50024000 0x4000 ESDHC 4 */
274 reg = <0x50024000 0x4000>;
280 /* 50028000 0x4000 SPDIF */
285 reg = <0x50030000 0x4000>;
291 /* 50034000 0x4000 SLM */
292 /* 50038000 0x4000 HSI2C */
294 /* 5003C000 0x4000 SPBA */
297 usbphy0: usbphy@0 {
309 reg = <0x53f80000 0x0200>;
317 reg = <0x53f80200 0x0200>;
325 reg = <0x53f80400 0x0200>;
332 reg = <0x53f80600 0x0200>;
340 reg = <0x53f80800 0x200>;
343 /* 53F98000 0x4000 WDOG1 */
346 reg = <0x53f98000 0x4000>;
352 /* 53F9C000 0x4000 WDOG2 (TZ) */
355 reg = <0x53f9c000 0x4000>;
361 /* 53F94000 0x4000 KPP */
364 reg = <0x53f94000 0x4000>;
370 /* 53FA0000 0x4000 GPT */
373 reg = <0x53fa0000 0x4000>;
379 /* 53FA4000 0x4000 SRTC */
383 reg = <0x53fa4000 0x4000>;
389 /* 53FA8000 0x4000 IOMUXC */
392 reg = <0x53fa8000 0x4000>;
397 /* 53FAC000 0x4000 EPIT1 */
400 reg = <0x53fac000 0x4000>;
406 /* 53FB0000 0x4000 EPIT2 */
409 reg = <0x53fb0000 0x4000>;
415 /* 53FB4000 0x4000 PWM1 */
418 reg = <0x53fb4000 0x4000>;
424 /* 53FB8000 0x4000 PWM2 */
427 reg = <0x53fb8000 0x4000>;
433 /* 53FBC000 0x4000 UART 1 */
436 reg = <0x53fbc000 0x4000>;
442 /* 53FC0000 0x4000 UART 2 */
445 reg = <0x53fc0000 0x4000>;
451 /* 53FF0000 0x4000 UART 4 */
454 reg = <0x53ff0000 0x4000>;
460 /* 53FD0000 0x4000 SRC */
463 reg = <0x53fd0000 0x4000>;
468 /* 53FD8000 0x4000 GPC */
471 reg = <0x53fd8000 0x4000>;
478 #size-cells = <0>;
481 reg = <0x53fec000 0x4000>;
495 /* 63F90000 0x4000 UART 5 */
498 reg = <0x63f90000 0x4000>;
504 /* 63F94000 0x4000 AHBMAX */
505 /* 63F98000 0x4000 IIM */
511 /* 63F9C000 0x4000 CSU */
517 /* 63FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */
526 /* 63FA4000 0x4000 OWIRE irq88 */
527 /* 63FA8000 0x4000 FIRI irq93 */
528 /* 63FAC000 0x4000 eCSPI2 */
531 #size-cells = <0>;
533 reg = <0x63fac000 0x4000>;
539 /* 63FB0000 0x4000 SDMA */
542 reg = <0x63fb0000 0x4000>;
547 /* 63FB4000 0x4000 SCC */
552 /* 63FB8000 0x4000 ROMCP */
553 /* 63FBC000 0x4000 RTIC */
559 /* 63FC0000 0x4000 CSPI */
562 #size-cells = <0>;
564 reg = <0x63fc0000 0x4000>;
570 /* 63FC4000 0x4000 I2C2 */
573 #size-cells = <0>;
575 reg = <0x63fc4000 0x4000>;
581 /* 63FC8000 0x4000 I2C1 */
584 #size-cells = <0>;
586 reg = <0x63fc8000 0x4000>;
592 /* 63FCC000 0x4000 SSI1 */
596 reg = <0x63fcc000 0x4000>;
602 /* 63FD0000 0x4000 AUDMUX */
605 reg = <0x63fd4000 0x4000>;
609 /* 63FD8000 0x4000 EXTMC */
618 /* 83FE4000 0x4000 SIM */
622 /* 63FD_C000 0x4000 apb2ip_pl301_2x2 */
623 /* 63FE_0000 0x4000 apb2ip_pl301_4x1 */
624 /* 63FE4000 0x4000 MLB */
625 /* 63FE8000 0x4000 SSI3 */
629 reg = <0x63fe8000 0x4000>;
635 /* 63FEC000 0x4000 FEC */
638 reg = <0x63fec000 0x4000>;
644 /* 63FF0000 0x4000 TVE */
646 /* 63FF4000 0x4000 VPU */
650 /* 63FF8000 0x4000 SAHARA */
651 /* 19 SAHARA SAHARA host 0 (TrustZone) Intr */
664 reg = <0x10000000 0x4000>;
673 0x1E000000 0x08000 /* CM */
674 0x1E008000 0x08000 /* IDMAC */
675 0x1E018000 0x08000 /* DP */
676 0x1E020000 0x08000 /* IC */
677 0x1E028000 0x08000 /* IRT */
678 0x1E030000 0x08000 /* CSI0 */
679 0x1E038000 0x08000 /* CSI1 */
680 0x1E040000 0x08000 /* DI0 */
681 0x1E048000 0x08000 /* DI1 */
682 0x1E050000 0x08000 /* SMFC */
683 0x1E058000 0x08000 /* DC */
684 0x1E060000 0x08000 /* DMFC */
685 0x1E068000 0x08000 /* VDI */
686 0x1F000000 0x20000 /* CPMEM */
687 0x1F020000 0x20000 /* LUT */
688 0x1F040000 0x20000 /* SRM */
689 0x1F060000 0x20000 /* TPM */
690 0x1F080000 0x20000 /* DCTMPL */