Lines Matching +full:0 +full:- +full:rtic
34 #address-cells = <1>;
35 #size-cells = <1>;
43 #address-cells = <1>;
44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0x0>;
50 d-cache-line-size = <32>;
51 i-cache-line-size = <32>;
52 d-cache-size = <0x8000>;
53 i-cache-size = <0x8000>;
54 l2-cache-line-size = <32>;
55 l2-cache-line = <0x40000>;
56 timebase-frequency = <0>;
57 bus-frequency = <0>;
58 clock-frequency = <0>;
62 localbus@0fffc000 {
63 compatible = "simple-bus";
64 #address-cells = <1>;
65 #size-cells = <1>;
70 tzic: tz-interrupt-controller@0fffc000 {
71 compatible = "fsl,imx53-tzic", "fsl,tzic";
72 interrupt-controller;
73 #interrupt-cells = <1>;
74 reg = <0x0fffc000 0x00004000>;
87 * 0FFFC000 0FFFCFFF 0x4000 TZIC
92 compatible = "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 interrupt-parent = <&tzic>;
99 compatible = "fsl,aips-bus", "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 interrupt-parent = <&tzic>;
106 /* 53FD4000 0x4000 CCM */
108 compatible = "fsl,imx53-ccm";
109 /* 63F80000 0x4000 DPLLIP1 */
110 /* 63F84000 0x4000 DPLLIP2 */
111 /* 63F88000 0x4000 DPLLIP3 */
112 reg = <0x53fd4000 0x4000
113 0x63F80000 0x4000
114 0x63F84000 0x4000
115 0x63F88000 0x4000>;
116 interrupt-parent = <&tzic>;
122 * GPIO modules moved up - to have it attached for
125 /* 53F84000 0x4000 GPIO1 */
127 compatible = "fsl,imx53-gpio";
128 reg = <0x53f84000 0x4000>;
129 interrupt-parent = <&tzic>;
132 gpio-controller;
133 #gpio-cells = <2>;
134 interrupt-controller;
135 #interrupt-cells = <1>;
138 /* 53F88000 0x4000 GPIO2 */
140 compatible = "fsl,imx53-gpio";
141 reg = <0x53f88000 0x4000>;
142 interrupt-parent = <&tzic>;
144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <1>;
150 /* 53F8C000 0x4000 GPIO3 */
152 compatible = "fsl,imx53-gpio";
153 reg = <0x53f8c000 0x4000>;
154 interrupt-parent = <&tzic>;
156 gpio-controller;
157 #gpio-cells = <2>;
158 interrupt-controller;
159 #interrupt-cells = <1>;
162 /* 53F90000 0x4000 GPIO4 */
164 compatible = "fsl,imx53-gpio";
165 reg = <0x53f90000 0x4000>;
166 interrupt-parent = <&tzic>;
168 gpio-controller;
169 #gpio-cells = <2>;
170 interrupt-controller;
171 #interrupt-cells = <1>;
174 /* 53FDC000 0x4000 GPIO5 */
176 compatible = "fsl,imx53-gpio";
177 reg = <0x53fdc000 0x4000>;
178 interrupt-parent = <&tzic>;
180 gpio-controller;
181 #gpio-cells = <2>;
182 interrupt-controller;
183 #interrupt-cells = <1>;
186 /* 53FE0000 0x4000 GPIO6 */
188 compatible = "fsl,imx53-gpio";
189 reg = <0x53fe0000 0x4000>;
190 interrupt-parent = <&tzic>;
192 gpio-controller;
193 #gpio-cells = <2>;
194 interrupt-controller;
195 #interrupt-cells = <1>;
198 /* 53FE4000 0x4000 GPIO5 */
200 compatible = "fsl,imx53-gpio";
201 reg = <0x53fe4000 0x4000>;
202 interrupt-parent = <&tzic>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
207 #interrupt-cells = <1>;
211 compatible = "fsl,spba-bus", "simple-bus";
212 #address-cells = <1>;
213 #size-cells = <1>;
214 interrupt-parent = <&tzic>;
217 /* 50004000 0x4000 ESDHC 1 */
219 compatible = "fsl,imx53-esdhc";
220 reg = <0x50004000 0x4000>;
221 interrupt-parent = <&tzic>; interrupts = <1>;
225 /* 50008000 0x4000 ESDHC 2 */
227 compatible = "fsl,imx53-esdhc";
228 reg = <0x50008000 0x4000>;
229 interrupt-parent = <&tzic>; interrupts = <2>;
233 /* 5000C000 0x4000 UART 3 */
235 compatible = "fsl,imx53-uart", "fsl,imx-uart";
236 reg = <0x5000c000 0x4000>;
237 interrupt-parent = <&tzic>;
242 /* 50010000 0x4000 eCSPI1 */
244 #address-cells = <1>;
245 #size-cells = <0>;
246 compatible = "fsl,imx53-ecspi";
247 reg = <0x50010000 0x4000>;
248 interrupt-parent = <&tzic>;
253 /* 50014000 0x4000 SSI2 irq30 */
255 compatible = "fsl,imx53-ssi";
256 reg = <0x50014000 0x4000>;
257 interrupt-parent = <&tzic>;
262 /* 50020000 0x4000 ESDHC 3 */
264 compatible = "fsl,imx53-esdhc";
265 reg = <0x50020000 0x4000>;
266 interrupt-parent = <&tzic>;
271 /* 50024000 0x4000 ESDHC 4 */
273 compatible = "fsl,imx53-esdhc";
274 reg = <0x50024000 0x4000>;
275 interrupt-parent = <&tzic>;
280 /* 50028000 0x4000 SPDIF */
284 compatible = "fsl,imx53-ata";
285 reg = <0x50030000 0x4000>;
286 interrupt-parent = <&tzic>;
291 /* 50034000 0x4000 SLM */
292 /* 50038000 0x4000 HSI2C */
293 /* 64 HS-I2C */
294 /* 5003C000 0x4000 SPBA */
297 usbphy0: usbphy@0 {
298 compatible = "usb-nop-xceiv";
303 compatible = "usb-nop-xceiv";
308 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
309 reg = <0x53f80000 0x0200>;
316 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
317 reg = <0x53f80200 0x0200>;
324 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
325 reg = <0x53f80400 0x0200>;
331 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
332 reg = <0x53f80600 0x0200>;
338 #index-cells = <1>;
339 compatible = "fsl,imx53-usbmisc";
340 reg = <0x53f80800 0x200>;
343 /* 53F98000 0x4000 WDOG1 */
345 compatible = "fsl,imx53-wdt";
346 reg = <0x53f98000 0x4000>;
347 interrupt-parent = <&tzic>;
352 /* 53F9C000 0x4000 WDOG2 (TZ) */
354 compatible = "fsl,imx53-wdt";
355 reg = <0x53f9c000 0x4000>;
356 interrupt-parent = <&tzic>;
361 /* 53F94000 0x4000 KPP */
363 compatible = "fsl,imx53-kpp";
364 reg = <0x53f94000 0x4000>;
365 interrupt-parent = <&tzic>;
370 /* 53FA0000 0x4000 GPT */
372 compatible = "fsl,imx53-gpt";
373 reg = <0x53fa0000 0x4000>;
374 interrupt-parent = <&tzic>;
379 /* 53FA4000 0x4000 SRTC */
382 compatible = "fsl,imx53-srtc";
383 reg = <0x53fa4000 0x4000>;
384 interrupt-parent = <&tzic>;
389 /* 53FA8000 0x4000 IOMUXC */
391 compatible = "fsl,imx53-iomux";
392 reg = <0x53fa8000 0x4000>;
393 interrupt-parent = <&tzic>;
397 /* 53FAC000 0x4000 EPIT1 */
399 compatible = "fsl,imx53-epit";
400 reg = <0x53fac000 0x4000>;
401 interrupt-parent = <&tzic>;
406 /* 53FB0000 0x4000 EPIT2 */
408 compatible = "fsl,imx53-epit";
409 reg = <0x53fb0000 0x4000>;
410 interrupt-parent = <&tzic>;
415 /* 53FB4000 0x4000 PWM1 */
417 compatible = "fsl,imx53-pwm";
418 reg = <0x53fb4000 0x4000>;
419 interrupt-parent = <&tzic>;
424 /* 53FB8000 0x4000 PWM2 */
426 compatible = "fsl,imx53-pwm";
427 reg = <0x53fb8000 0x4000>;
428 interrupt-parent = <&tzic>;
433 /* 53FBC000 0x4000 UART 1 */
435 compatible = "fsl,imx53-uart", "fsl,imx-uart";
436 reg = <0x53fbc000 0x4000>;
437 interrupt-parent = <&tzic>;
442 /* 53FC0000 0x4000 UART 2 */
444 compatible = "fsl,imx53-uart", "fsl,imx-uart";
445 reg = <0x53fc0000 0x4000>;
446 interrupt-parent = <&tzic>;
451 /* 53FF0000 0x4000 UART 4 */
453 compatible = "fsl,imx53-uart", "fsl,imx-uart";
454 reg = <0x53ff0000 0x4000>;
455 interrupt-parent = <&tzic>;
460 /* 53FD0000 0x4000 SRC */
462 compatible = "fsl,imx53-src";
463 reg = <0x53fd0000 0x4000>;
464 interrupt-parent = <&tzic>;
468 /* 53FD8000 0x4000 GPC */
470 compatible = "fsl,imx53-gpc";
471 reg = <0x53fd8000 0x4000>;
472 interrupt-parent = <&tzic>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c",
480 "fsl,imx-i2c";
481 reg = <0x53fec000 0x4000>;
482 interrupt-parent = <&tzic>;
489 compatible = "fsl,aips-bus", "simple-bus";
490 #address-cells = <1>;
491 #size-cells = <1>;
492 interrupt-parent = <&tzic>;
495 /* 63F90000 0x4000 UART 5 */
497 compatible = "fsl,imx53-uart", "fsl,imx-uart";
498 reg = <0x63f90000 0x4000>;
499 interrupt-parent = <&tzic>;
504 /* 63F94000 0x4000 AHBMAX */
505 /* 63F98000 0x4000 IIM */
511 /* 63F9C000 0x4000 CSU */
517 /* 63FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */
521 /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */
522 /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */
523 /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */
524 /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */
526 /* 63FA4000 0x4000 OWIRE irq88 */
527 /* 63FA8000 0x4000 FIRI irq93 */
528 /* 63FAC000 0x4000 eCSPI2 */
530 #address-cells = <1>;
531 #size-cells = <0>;
532 compatible = "fsl,imx53-ecspi";
533 reg = <0x63fac000 0x4000>;
534 interrupt-parent = <&tzic>;
539 /* 63FB0000 0x4000 SDMA */
541 compatible = "fsl,imx53-sdma";
542 reg = <0x63fb0000 0x4000>;
543 interrupt-parent = <&tzic>;
547 /* 63FB4000 0x4000 SCC */
550 /* 23 SCC Regular (Non-Secure) Interrupt. */
552 /* 63FB8000 0x4000 ROMCP */
553 /* 63FBC000 0x4000 RTIC */
555 * 26 RTIC RTIC (Trust Zone) Interrupt Request.
556 * Indicates that the RTIC has completed hashing the
559 /* 63FC0000 0x4000 CSPI */
561 #address-cells = <1>;
562 #size-cells = <0>;
563 compatible = "fsl,imx53-cspi";
564 reg = <0x63fc0000 0x4000>;
565 interrupt-parent = <&tzic>;
570 /* 63FC4000 0x4000 I2C2 */
572 #address-cells = <1>;
573 #size-cells = <0>;
574 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
575 reg = <0x63fc4000 0x4000>;
576 interrupt-parent = <&tzic>;
581 /* 63FC8000 0x4000 I2C1 */
583 #address-cells = <1>;
584 #size-cells = <0>;
585 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
586 reg = <0x63fc8000 0x4000>;
587 interrupt-parent = <&tzic>;
592 /* 63FCC000 0x4000 SSI1 */
593 /* 29 SSI1 SSI-1 Interrupt Request */
595 compatible = "fsl,imx53-ssi";
596 reg = <0x63fcc000 0x4000>;
597 interrupt-parent = <&tzic>;
602 /* 63FD0000 0x4000 AUDMUX */
604 compatible = "fsl,imx53-audmux";
605 reg = <0x63fd4000 0x4000>;
609 /* 63FD8000 0x4000 EXTMC */
618 /* 83FE4000 0x4000 SIM */
622 /* 63FD_C000 0x4000 apb2ip_pl301_2x2 */
623 /* 63FE_0000 0x4000 apb2ip_pl301_4x1 */
624 /* 63FE4000 0x4000 MLB */
625 /* 63FE8000 0x4000 SSI3 */
626 /* 96 SSI3 SSI-3 Interrupt Request */
628 compatible = "fsl,imx51-ssi";
629 reg = <0x63fe8000 0x4000>;
630 interrupt-parent = <&tzic>;
635 /* 63FEC000 0x4000 FEC */
637 compatible = "fsl,imx53-fec";
638 reg = <0x63fec000 0x4000>;
639 interrupt-parent = <&tzic>;
644 /* 63FF0000 0x4000 TVE */
646 /* 63FF4000 0x4000 VPU */
650 /* 63FF8000 0x4000 SAHARA */
651 /* 19 SAHARA SAHARA host 0 (TrustZone) Intr */
652 /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr */
657 compatible = "simple-bus";
658 #address-cells = <1>;
659 #size-cells = <1>;
663 compatible = "fsl,imx53-ata";
664 reg = <0x10000000 0x4000>;
665 interrupt-parent = <&tzic>;
673 0x1E000000 0x08000 /* CM */
674 0x1E008000 0x08000 /* IDMAC */
675 0x1E018000 0x08000 /* DP */
676 0x1E020000 0x08000 /* IC */
677 0x1E028000 0x08000 /* IRT */
678 0x1E030000 0x08000 /* CSI0 */
679 0x1E038000 0x08000 /* CSI1 */
680 0x1E040000 0x08000 /* DI0 */
681 0x1E048000 0x08000 /* DI1 */
682 0x1E050000 0x08000 /* SMFC */
683 0x1E058000 0x08000 /* DC */
684 0x1E060000 0x08000 /* DMFC */
685 0x1E068000 0x08000 /* VDI */
686 0x1F000000 0x20000 /* CPMEM */
687 0x1F020000 0x20000 /* LUT */
688 0x1F040000 0x20000 /* SRM */
689 0x1F060000 0x20000 /* TPM */
690 0x1F080000 0x20000 /* DCTMPL */
692 interrupt-parent = <&tzic>;