Lines Matching +full:120 +full:- +full:db

3  * Copyright (c) 2010-2011 Semihalf
27 * Marvell DB-78460 Device Tree Source.
30 /dts-v1/;
33 model = "mrvl,DB-78460";
34 #address-cells = <1>;
35 #size-cells = <1>;
42 #address-cells = <1>;
43 #size-cells = <0>;
49 d-cache-line-size = <32>; // 32 bytes
50 i-cache-line-size = <32>; // 32 bytes
51 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <0x8000>; // L1, 32K
53 timebase-frequency = <0>;
54 bus-frequency = <200000000>;
55 clock-frequency = <0>;
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "simple-bus";
69 bus-frequency = <0>;
73 interrupt-controller;
74 #address-cells = <0>;
75 #interrupt-cells = <1>;
86 compatible = "marvell,armada-xp-timer";
89 interrupt-parent = <&MPIC>;
90 mrvl,has-wdt;
94 #address-cells = <1>;
95 #size-cells = <0>;
99 interrupt-parent = <&MPIC>;
103 #address-cells = <1>;
104 #size-cells = <0>;
108 interrupt-parent = <&MPIC>;
112 compatible = "snps,dw-apb-uart";
114 reg-shift = <2>;
115 current-speed = <115200>;
116 clock-frequency = <0>;
118 interrupt-parent = <&MPIC>;
122 compatible = "snps,dw-apb-uart";
124 reg-shift = <2>;
125 current-speed = <115200>;
126 clock-frequency = <0>;
128 interrupt-parent = <&MPIC>;
132 compatible = "snps,dw-apb-uart";
134 reg-shift = <2>;
135 current-speed = <115200>;
136 clock-frequency = <0>;
138 interrupt-parent = <&MPIC>;
142 compatible = "snps,dw-apb-uart";
144 reg-shift = <2>;
145 current-speed = <115200>;
146 clock-frequency = <0>;
148 interrupt-parent = <&MPIC>;
152 #pin-cells = <2>;
155 pin-count = <68>;
156 pin-map = <
228 compatible = "mrvl,usb-ehci", "usb-ehci";
231 interrupt-parent = <&MPIC>;
235 compatible = "mrvl,usb-ehci", "usb-ehci";
238 interrupt-parent = <&MPIC>;
242 compatible = "mrvl,usb-ehci", "usb-ehci";
245 interrupt-parent = <&MPIC>;
249 #address-cells = <1>;
250 #size-cells = <1>;
255 local-mac-address = [ 00 04 01 07 84 60 ];
257 interrupt-parent = <&MPIC>;
258 phy-handle = <&phy0>;
259 has-neta;
262 #address-cells = <1>;
263 #size-cells = <0>;
266 phy0: ethernet-phy@0 {
269 phy1: ethernet-phy@1 {
272 phy2: ethernet-phy@2 {
275 phy3: ethernet-phy@3 {
285 interrupt-parent = <&MPIC>;
292 #interrupt-cells = <1>;
293 #size-cells = <2>;
294 #address-cells = <3>;
296 bus-range = <0 255>;
299 clock-frequency = <33333333>;
300 interrupt-parent = <&MPIC>;
301 interrupts = <120>;
302 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
303 interrupt-map = <
312 compatible = "mrvl,cesa-sram";