Lines Matching +full:0 +full:x20a00
43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0x0>;
51 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <0x8000>; // L1, 32K
53 timebase-frequency = <0>;
55 clock-frequency = <0>;
61 reg = <0x0 0x80000000>; // 2G at 0x0
68 ranges = <0x0 0xd0000000 0x00100000>;
69 bus-frequency = <0>;
74 #address-cells = <0>;
76 reg = <0x20a00 0x500 0x21870 0x58 0x20400 0x100>;
82 reg = <0x10300 0x08>;
87 reg = <0x21840 0x30>;
95 #size-cells = <0>;
97 reg = <0x11000 0x20>;
104 #size-cells = <0>;
106 reg = <0x11100 0x20>;
113 reg = <0x12000 0x20>;
116 clock-frequency = <0>;
123 reg = <0x12100 0x20>;
126 clock-frequency = <0>;
133 reg = <0x12200 0x20>;
136 clock-frequency = <0>;
143 reg = <0x12300 0x20>;
146 clock-frequency = <0>;
154 reg = <0x18000 0x34>;
157 0 1 /* MPP[0]: GE1_TXCLK */
161 4 1 /* MPP[4]: GE1_TXD[0] */
165 8 1 /* MPP[8]: GE1_RXD[0] */
181 24 0
182 25 0
183 26 0
184 27 0
186 29 0
197 40 0
205 48 0
214 57 0
229 reg = <0x50000 0x1000>;
236 reg = <0x51000 0x1000>;
243 reg = <0x52000 0x1000>;
253 reg = <0x72000 0x2000>;
254 ranges = <0x0 0x72000 0x2000>;
261 mdio@0 {
263 #size-cells = <0>;
266 phy0: ethernet-phy@0 {
267 reg = <0x0>;
270 reg = <0x1>;
273 reg = <0x19>;
276 reg = <0x1b>;
283 reg = <0xA0000 0x6000>;
295 reg = <0xd0040000 0x2000>;
296 bus-range = <0 255>;
297 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
298 0x01000000 0x0 0x00000000 0xa0000000 0x0 0x08000000>;
302 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
304 0x0800 0x0 0x0 0x1 &MPIC 0x3A
305 0x0800 0x0 0x0 0x2 &MPIC 0x3A
306 0x0800 0x0 0x0 0x3 &MPIC 0x3A
307 0x0800 0x0 0x0 0x4 &MPIC 0x3A
313 reg = <0xffff0000 0x00010000>;