Lines Matching +full:cortex +full:- +full:a15
1 /*-
28 /dts-v1/;
32 #address-cells = <1>;
33 #size-cells = <1>;
40 #address-cells = <1>;
41 #size-cells = <0>;
45 compatible = "arm,cortex-a15";
47 d-cache-line-size = <64>; // 64 bytes
48 i-cache-line-size = <64>; // 64 bytes
49 d-cache-size = <0x8000>; // L1, 32K
50 i-cache-size = <0x8000>; // L1, 32K
51 timebase-frequency = <0>;
52 bus-frequency = <375000000>;
53 clock-frequency = <0>;
58 compatible = "arm,cortex-a15";
60 d-cache-line-size = <64>; // 64 bytes
61 i-cache-line-size = <64>; // 64 bytes
62 d-cache-size = <0x8000>; // L1, 32K
63 i-cache-size = <0x8000>; // L1, 32K
64 timebase-frequency = <0>;
65 bus-frequency = <375000000>;
66 clock-frequency = <0>;
71 compatible = "arm,cortex-a15";
73 d-cache-line-size = <64>; // 64 bytes
74 i-cache-line-size = <64>; // 64 bytes
75 d-cache-size = <0x8000>; // L1, 32K
76 i-cache-size = <0x8000>; // L1, 32K
77 timebase-frequency = <0>;
78 bus-frequency = <375000000>;
79 clock-frequency = <0>;
84 compatible = "arm,cortex-a15";
86 d-cache-line-size = <64>; // 64 bytes
87 i-cache-line-size = <64>; // 64 bytes
88 d-cache-size = <0x8000>; // L1, 32K
89 i-cache-size = <0x8000>; // L1, 32K
90 timebase-frequency = <0>;
91 bus-frequency = <375000000>;
92 clock-frequency = <0>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104 compatible = "simple-bus";
106 bus-frequency = <0>;
108 MPIC: interrupt-controller {
112 interrupt-controller;
113 #address-cells = <0>;
114 #interrupt-cells = <3>;
117 // 1 = low-to-high edge triggered
118 // 2 = high-to-low edge triggered
119 // 4 = active high level-sensitive
120 // 8 = active low level-sensitive
121 // The hardware only supports active-high-level or rising-edge.
129 interrupt-parent = <&MPIC>;
130 clock-frequency = <375000000>;
134 compatible = "annapurna-labs,al-cpu-resume";
139 compatible = "annapurna-labs,al-ccu";
145 compatible = "annapurna-labs,al-nb-service";
151 interrupt-parent = <&MPIC>;
157 interrupt-parent = <&MPIC>;
162 compatible = "annapurna-labs,al-serdes";
169 reg-shift = <2>;
170 current-speed = <115200>;
171 clock-frequency = <375000000>;
173 interrupt-parent = <&MPIC>;
179 compatible = "annapurna-labs,al-msix";
180 #address-cells = <2>;
181 #size-cells = <1>;
184 interrupt-parent = <&MPIC>;
187 pcie-internal {
188 compatible = "annapurna-labs,al-internal-pcie";
190 #size-cells = <2>;
191 #address-cells = <3>;
193 interrupt-parent = <&MPIC>;
194 interrupt-map-mask = <0xf800 0 0 7>;
195 interrupt-map = <0x3000 0 0 1 &MPIC 0 32 4>, // USB adapter
199 msi-parent = <&msix>;
202 // - ECAM - non prefetchable config space
203 // - 32 bit non prefetchable memory space
207 bus-range = <0x00 0x00>;
211 // leads to kernel panic because u-boot disables PCIe controller if no link
214 pcie-external0 {
215 compatible = "annapurna-labs,al-external-pcie";
218 #size-cells = <2>;
219 #address-cells = <3>;
220 interrupt-parent = <&MPIC>;
221 interrupt-map-mask = <0x00 0 0 7>;
222 interrupt-map = <0x0000 0 0 1 &MPIC 0 40 4>;
226 // - ECAM - non prefetchable config space: 2MB
227 // - IO - IO port space 64KB, reserve 64KB from target memory windows
229 // - 32 bit non prefetchable memory space: 128MB - 64KB
235 bus-range = <0x00 0xff>;
239 pcie-external1 {
240 compatible = "annapurna-labs,al-external-pcie";
243 #size-cells = <2>;
244 #address-cells = <3>;
245 interrupt-parent = <&MPIC>;
246 interrupt-map-mask = <0x0 0 0 7>;
247 interrupt-map = <0x0000 0 0 1 &MPIC 0 41 4>;
250 // - ECAM - non prefetchable config space: 2MB
251 // - IO - IO port space 64KB, reserve 64KB from target memory windows
253 // - 32 bit non prefetchable memory space: 64MB - 64KB
258 bus-range = <0x00 0xff>;