Lines Matching +full:0 +full:x8000
41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0x0>;
49 d-cache-size = <0x8000>; // L1, 32K
50 i-cache-size = <0x8000>; // L1, 32K
51 timebase-frequency = <0>;
53 clock-frequency = <0>;
59 reg = <0x0>;
62 d-cache-size = <0x8000>; // L1, 32K
63 i-cache-size = <0x8000>; // L1, 32K
64 timebase-frequency = <0>;
66 clock-frequency = <0>;
72 reg = <0x0>;
75 d-cache-size = <0x8000>; // L1, 32K
76 i-cache-size = <0x8000>; // L1, 32K
77 timebase-frequency = <0>;
79 clock-frequency = <0>;
85 reg = <0x0>;
88 d-cache-size = <0x8000>; // L1, 32K
89 i-cache-size = <0x8000>; // L1, 32K
90 timebase-frequency = <0>;
92 clock-frequency = <0>;
98 reg = <0x00100000 0x7ff00000>; // 2047MB at 1MB
105 ranges = <0x0 0xfb000000 0x03000000>;
106 bus-frequency = <0>;
110 reg = < 0x1000 0x1000 >, /* Distributor Registers */
111 < 0x2000 0x2000 >; /* CPU Interface Registers */
113 #address-cells = <0>;
116 // In intr[2], bits[3:0] are trigger type and level flags.
127 reg = <0x02890000 0x1000>;
128 interrupts = <0 9 4>;
135 reg = <0x00ff5ec0 0x30>;
140 reg = <0x00090000 0x10000>;
146 reg = <0x00070000 0x10000>;
147 interrupts = <0 32 4>,
148 <0 33 4>,
149 <0 34 4>,
150 <0 35 4>;
156 reg = <0x288c000 0x1000>;
163 reg = <0x28c0000 0x1000>;
168 reg = <0x2883000 0x20>;
172 interrupts = <0 17 4>;
182 reg = <0xfbe00000 0x100000>;
183 interrupts = <0 96 1 0 159 1>;
192 reg = <0xfbc00000 0x100000>;
194 interrupt-map-mask = <0xf800 0 0 7>;
195 interrupt-map = <0x3000 0 0 1 &MPIC 0 32 4>, // USB adapter
196 <0x3800 0 0 1 &MPIC 0 36 4>,
197 <0x4000 0 0 1 &MPIC 0 43 4>, // SATA 0 (PCIe expander)
198 <0x4800 0 0 1 &MPIC 0 44 1>; // SATA 1 (onboard)
204 ranges = <0x00000000 0x0 0xfbc00000 0xfbc00000 0x0 0x100000
205 0x02000000 0x0 0xfe000000 0xfe000000 0x0 0x1000000>;
207 bus-range = <0x00 0x00>;
213 /* // External PCIe Controller 0
216 reg = <0xfd800000 0x00020000>;
221 interrupt-map-mask = <0x00 0 0 7>;
222 interrupt-map = <0x0000 0 0 1 &MPIC 0 40 4>;
225 // Controller 0:
228 // real IO address on the pci bus starts at 0x10000
231 ranges = <0x00000000 0x0 0xfb600000 0xfb600000 0x0 0x00200000
232 0x01000000 0x0 0x00010000 0xe0000000 0x0 0x00010000
233 0x02000000 0x0 0xe1000000 0xe1000000 0x0 0x06f00000>;
235 bus-range = <0x00 0xff>;
241 reg = <0xfd820000 0x00020000>;
246 interrupt-map-mask = <0x0 0 0 7>;
247 interrupt-map = <0x0000 0 0 1 &MPIC 0 41 4>;
252 // real IO address on the pci bus starts at 0x20000
254 ranges = <0x00000000 0x0 0xfb800000 0xfb800000 0x0 0x00200000
255 0x01000000 0x0 0x00020000 0xe8000000 0x0 0x00010000
256 0x02000000 0x0 0xe8100000 0xe8100000 0x0 0x02ff0000>;
258 bus-range = <0x00 0xff>;