Lines Matching +full:0 +full:x0040
35 #define XL_EE_READ 0x0080 /* read, 5 bit address */
36 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */
37 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
38 #define XL_EE_EWEN 0x0030 /* erase, no data needed */
39 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
40 #define XL_EE_BUSY 0x8000
42 #define XL_EE_EADDR0 0x00 /* station address, first word */
43 #define XL_EE_EADDR1 0x01 /* station address, next word, */
44 #define XL_EE_EADDR2 0x02 /* station address, last word */
45 #define XL_EE_PRODID 0x03 /* product ID code */
46 #define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */
47 #define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */
48 #define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */
49 #define XL_EE_MFG_ID 0x07
50 #define XL_EE_PCI_PARM 0x08
51 #define XL_EE_ROM_ONFO 0x09
52 #define XL_EE_OEM_ADR0 0x0A
53 #define XL_EE_OEM_ADR1 0x0B
54 #define XL_EE_OEM_ADR2 0x0C
55 #define XL_EE_SOFTINFO1 0x0D
56 #define XL_EE_COMPAT 0x0E
57 #define XL_EE_SOFTINFO2 0x0F
58 #define XL_EE_CAPS 0x10 /* capabilities word */
59 #define XL_EE_RSVD0 0x11
60 #define XL_EE_ICFG_0 0x12
61 #define XL_EE_ICFG_1 0x13
62 #define XL_EE_RSVD1 0x14
63 #define XL_EE_SOFTINFO3 0x15
64 #define XL_EE_RSVD_2 0x16
69 #define XL_CAPS_PNP 0x0001
70 #define XL_CAPS_FULL_DUPLEX 0x0002
71 #define XL_CAPS_LARGE_PKTS 0x0004
72 #define XL_CAPS_SLAVE_DMA 0x0008
73 #define XL_CAPS_SECOND_DMA 0x0010
74 #define XL_CAPS_FULL_BM 0x0020
75 #define XL_CAPS_FRAG_BM 0x0040
76 #define XL_CAPS_CRC_PASSTHRU 0x0080
77 #define XL_CAPS_TXDONE 0x0100
78 #define XL_CAPS_NO_TXLENGTH 0x0200
79 #define XL_CAPS_RX_REPEAT 0x0400
80 #define XL_CAPS_SNOOPING 0x0800
81 #define XL_CAPS_100MBPS 0x1000
82 #define XL_CAPS_PWRMGMT 0x2000
87 #define XL_SINFO2_FIXED_BCAST_RX_BUG 0x0002
88 #define XL_SINFO2_FIXED_ENDEC_LOOP_BUG 0x0004
89 #define XL_SINFO2_AUX_WOL_CON 0x0008
90 #define XL_SINFO2_PME_PULSED 0x0010
91 #define XL_SINFO2_FIXED_MWI_BUG 0x0020
92 #define XL_SINFO2_WOL_AFTER_PWR_LOSS 0x0040
93 #define XL_SINFO2_AUTO_RST_TO_D0 0x0080
101 #define XL_COMMAND 0x0E
102 #define XL_STATUS 0x0E
104 #define XL_TX_STATUS 0x1B
105 #define XL_TX_FREE 0x1C
106 #define XL_DMACTL 0x20
107 #define XL_DOWNLIST_PTR 0x24
108 #define XL_DOWN_POLL 0x2D /* 3c90xB only */
109 #define XL_TX_FREETHRESH 0x2F
110 #define XL_UPLIST_PTR 0x38
111 #define XL_UPLIST_STATUS 0x30
112 #define XL_UP_POLL 0x3D /* 3c90xB only */
114 #define XL_PKTSTAT_UP_STALLED 0x00002000
115 #define XL_PKTSTAT_UP_ERROR 0x00004000
116 #define XL_PKTSTAT_UP_CMPLT 0x00008000
118 #define XL_DMACTL_DN_CMPLT_REQ 0x00000002
119 #define XL_DMACTL_DOWN_STALLED 0x00000004
120 #define XL_DMACTL_UP_CMPLT 0x00000008
121 #define XL_DMACTL_DOWN_CMPLT 0x00000010
122 #define XL_DMACTL_UP_RX_EARLY 0x00000020
123 #define XL_DMACTL_ARM_COUNTDOWN 0x00000040
124 #define XL_DMACTL_DOWN_INPROG 0x00000080
125 #define XL_DMACTL_COUNTER_SPEED 0x00000100
126 #define XL_DMACTL_DOWNDOWN_MODE 0x00000200
127 #define XL_DMACTL_UP_ALTSEQ_DIS 0x00010000 /* 3c90xB/3c90xC */
128 #define XL_DMACTL_DOWN_ALTSEQ_DIS 0x00020000 /* 3c90xC only */
129 #define XL_DMACTL_DEFEAT_MWI 0x00100000 /* 3c90xB/3c90xC */
130 #define XL_DMACTL_DEFEAT_MRL 0x00100000 /* 3c90xB/3c90xC */
131 #define XL_DMACTL_UP_OVERRUN_DISC_DIS 0x00200000 /* 3c90xB/3c90xC */
132 #define XL_DMACTL_TARGET_ABORT 0x40000000
133 #define XL_DMACTL_MASTER_ABORT 0x80000000
139 #define XL_CMD_RESET 0x0000 /* mustwait */
140 #define XL_CMD_WINSEL 0x0800
141 #define XL_CMD_COAX_START 0x1000
142 #define XL_CMD_RX_DISABLE 0x1800
143 #define XL_CMD_RX_ENABLE 0x2000
144 #define XL_CMD_RX_RESET 0x2800 /* mustwait */
145 #define XL_CMD_UP_STALL 0x3000 /* mustwait */
146 #define XL_CMD_UP_UNSTALL 0x3001
147 #define XL_CMD_DOWN_STALL 0x3002 /* mustwait */
148 #define XL_CMD_DOWN_UNSTALL 0x3003
149 #define XL_CMD_RX_DISCARD 0x4000
150 #define XL_CMD_TX_ENABLE 0x4800
151 #define XL_CMD_TX_DISABLE 0x5000
152 #define XL_CMD_TX_RESET 0x5800 /* mustwait */
153 #define XL_CMD_INTR_FAKE 0x6000
154 #define XL_CMD_INTR_ACK 0x6800
155 #define XL_CMD_INTR_ENB 0x7000
156 #define XL_CMD_STAT_ENB 0x7800
157 #define XL_CMD_RX_SET_FILT 0x8000
158 #define XL_CMD_RX_SET_THRESH 0x8800
159 #define XL_CMD_TX_SET_THRESH 0x9000
160 #define XL_CMD_TX_SET_START 0x9800
161 #define XL_CMD_DMA_UP 0xA000
162 #define XL_CMD_DMA_STOP 0xA001
163 #define XL_CMD_STATS_ENABLE 0xA800
164 #define XL_CMD_STATS_DISABLE 0xB000
165 #define XL_CMD_COAX_STOP 0xB800
167 #define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */
168 #define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */
170 #define XL_HASH_SET 0x0400
176 * which may be anything from 0 to 7.
178 #define XL_STAT_INTLATCH 0x0001 /* 0 */
179 #define XL_STAT_ADFAIL 0x0002 /* 1 */
180 #define XL_STAT_TX_COMPLETE 0x0004 /* 2 */
181 #define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */
182 #define XL_STAT_RX_COMPLETE 0x0010 /* 4 */
183 #define XL_STAT_RX_EARLY 0x0020 /* 5 */
184 #define XL_STAT_INTREQ 0x0040 /* 6 */
185 #define XL_STAT_STATSOFLOW 0x0080 /* 7 */
186 #define XL_STAT_DMADONE 0x0100 /* 8 first generation */
187 #define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */
188 #define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */
189 #define XL_STAT_UP_COMPLETE 0x0400 /* 10 */
190 #define XL_STAT_DMABUSY 0x0800 /* 11 first generation */
191 #define XL_STAT_CMDBUSY 0x1000 /* 12 */
201 * Window 0 registers
203 #define XL_W0_EE_DATA 0x0C
204 #define XL_W0_EE_CMD 0x0A
205 #define XL_W0_RSRC_CFG 0x08
206 #define XL_W0_ADDR_CFG 0x06
207 #define XL_W0_CFG_CTRL 0x04
209 #define XL_W0_PROD_ID 0x02
210 #define XL_W0_MFG_ID 0x00
216 #define XL_W1_TX_FIFO 0x10
218 #define XL_W1_FREE_TX 0x0C
219 #define XL_W1_TX_STATUS 0x0B
220 #define XL_W1_TX_TIMER 0x0A
221 #define XL_W1_RX_STATUS 0x08
222 #define XL_W1_RX_FIFO 0x00
227 #define XL_RXSTATUS_OVERRUN 0x01
228 #define XL_RXSTATUS_RUNT 0x02
229 #define XL_RXSTATUS_ALIGN 0x04
230 #define XL_RXSTATUS_CRC 0x08
231 #define XL_RXSTATUS_OVERSIZE 0x10
232 #define XL_RXSTATUS_DRIBBLE 0x20
237 #define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */
238 #define XL_TXSTATUS_OVERFLOW 0x04
239 #define XL_TXSTATUS_MAXCOLS 0x08
240 #define XL_TXSTATUS_UNDERRUN 0x10
241 #define XL_TXSTATUS_JABBER 0x20
242 #define XL_TXSTATUS_INTREQ 0x40
243 #define XL_TXSTATUS_COMPLETE 0x80
248 #define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */
249 #define XL_W2_STATION_MASK_HI 0x0A
250 #define XL_W2_STATION_MASK_MID 0x08
251 #define XL_W2_STATION_MASK_LO 0x06
252 #define XL_W2_STATION_ADDR_HI 0x04
253 #define XL_W2_STATION_ADDR_MID 0x02
254 #define XL_W2_STATION_ADDR_LO 0x00
256 #define XL_RESETOPT_FEATUREMASK (0x0001 | 0x0002 | 0x004)
257 #define XL_RESETOPT_D3RESETDIS 0x0008
258 #define XL_RESETOPT_DISADVFD 0x0010
259 #define XL_RESETOPT_DISADV100 0x0020
260 #define XL_RESETOPT_DISAUTONEG 0x0040
261 #define XL_RESETOPT_DEBUGMODE 0x0080
262 #define XL_RESETOPT_FASTAUTO 0x0100
263 #define XL_RESETOPT_FASTEE 0x0200
264 #define XL_RESETOPT_FORCEDCONF 0x0400
265 #define XL_RESETOPT_TESTPDTPDR 0x0800
266 #define XL_RESETOPT_TEST100TX 0x1000
267 #define XL_RESETOPT_TEST100RX 0x2000
269 #define XL_RESETOPT_INVERT_LED 0x0010
270 #define XL_RESETOPT_INVERT_MII 0x4000
275 #define XL_W3_INTERNAL_CFG 0x00
276 #define XL_W3_MAXPKTSIZE 0x04 /* 3c905B only */
277 #define XL_W3_RESET_OPT 0x08
278 #define XL_W3_FREE_TX 0x0C
279 #define XL_W3_FREE_RX 0x0A
280 #define XL_W3_MAC_CTRL 0x06
282 #define XL_ICFG_CONNECTOR_MASK 0x00F00000
285 #define XL_ICFG_RAMSIZE_MASK 0x00000007
286 #define XL_ICFG_RAMWIDTH 0x00000008
287 #define XL_ICFG_ROMSIZE_MASK (0x00000040 | 0x00000080)
288 #define XL_ICFG_DISABLE_BASSD 0x00000100
289 #define XL_ICFG_RAMLOC 0x00000200
290 #define XL_ICFG_RAMPART (0x00010000 | 0x00020000)
291 #define XL_ICFG_XCVRSEL (0x00100000 | 0x00200000 | 0x00400000)
292 #define XL_ICFG_AUTOSEL 0x01000000
294 #define XL_XCVR_10BT 0x00
295 #define XL_XCVR_AUI 0x01
296 #define XL_XCVR_RSVD_0 0x02
297 #define XL_XCVR_COAX 0x03
298 #define XL_XCVR_100BTX 0x04
299 #define XL_XCVR_100BFX 0x05
300 #define XL_XCVR_MII 0x06
301 #define XL_XCVR_RSVD_1 0x07
302 #define XL_XCVR_AUTO 0x08 /* 3c905B only */
304 #define XL_MACCTRL_DEFER_EXT_END 0x0001
305 #define XL_MACCTRL_DEFER_0 0x0002
306 #define XL_MACCTRL_DEFER_1 0x0004
307 #define XL_MACCTRL_DEFER_2 0x0008
308 #define XL_MACCTRL_DEFER_3 0x0010
309 #define XL_MACCTRL_DUPLEX 0x0020
310 #define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040
311 #define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 /* 3c905B only */
312 #define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 /* 3c905B only */
313 #define XL_MACCTRL_VLT_END 0x0200 /* 3c905B only */
320 #define XL_W3_MEDIA_OPT 0x08
322 #define XL_MEDIAOPT_BT4 0x0001 /* MII */
323 #define XL_MEDIAOPT_BTX 0x0002 /* on-chip */
324 #define XL_MEDIAOPT_BFX 0x0004 /* on-chip */
325 #define XL_MEDIAOPT_BT 0x0008 /* on-chip */
326 #define XL_MEDIAOPT_BNC 0x0010 /* on-chip */
327 #define XL_MEDIAOPT_AUI 0x0020 /* on-chip */
328 #define XL_MEDIAOPT_MII 0x0040 /* MII */
329 #define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */
331 #define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */
332 #define XL_MEDIAOPT_MASK 0x01FF
337 #define XL_W4_UPPERBYTESOK 0x0D
338 #define XL_W4_BADSSD 0x0C
339 #define XL_W4_MEDIA_STATUS 0x0A
340 #define XL_W4_PHY_MGMT 0x08
341 #define XL_W4_NET_DIAG 0x06
342 #define XL_W4_FIFO_DIAG 0x04
343 #define XL_W4_VCO_DIAG 0x02
345 #define XL_W4_CTRLR_STAT 0x08
346 #define XL_W4_TX_DIAG 0x00
348 #define XL_MII_CLK 0x01
349 #define XL_MII_DATA 0x02
350 #define XL_MII_DIR 0x04
352 #define XL_MEDIA_SQE 0x0008
353 #define XL_MEDIA_10TP 0x00C0
354 #define XL_MEDIA_LNK 0x0080
355 #define XL_MEDIA_LNKBEAT 0x0800
357 #define XL_MEDIASTAT_CRCSTRIP 0x0004
358 #define XL_MEDIASTAT_SQEENB 0x0008
359 #define XL_MEDIASTAT_COLDET 0x0010
360 #define XL_MEDIASTAT_CARRIER 0x0020
361 #define XL_MEDIASTAT_JABGUARD 0x0040
362 #define XL_MEDIASTAT_LINKBEAT 0x0080
363 #define XL_MEDIASTAT_JABDETECT 0x0200
364 #define XL_MEDIASTAT_POLREVERS 0x0400
365 #define XL_MEDIASTAT_LINKDETECT 0x0800
366 #define XL_MEDIASTAT_TXINPROG 0x1000
367 #define XL_MEDIASTAT_DCENB 0x4000
368 #define XL_MEDIASTAT_AUIDIS 0x8000
370 #define XL_NETDIAG_TEST_LOWVOLT 0x0001
372 (0x0002 | 0x0004 | 0x0008 | 0x0010 | 0x0020)
373 #define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040
374 #define XL_NETDIAG_STATS_ENABLED 0x0080
375 #define XL_NETDIAG_TX_FATALERR 0x0100
376 #define XL_NETDIAG_TRANSMITTING 0x0200
377 #define XL_NETDIAG_RX_ENABLED 0x0400
378 #define XL_NETDIAG_TX_ENABLED 0x0800
379 #define XL_NETDIAG_FIFO_LOOPBACK 0x1000
380 #define XL_NETDIAG_MAC_LOOPBACK 0x2000
381 #define XL_NETDIAG_ENDEC_LOOPBACK 0x4000
382 #define XL_NETDIAG_EXTERNAL_LOOP 0x8000
387 #define XL_W5_STAT_ENB 0x0C
388 #define XL_W5_INTR_ENB 0x0A
389 #define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */
390 #define XL_W5_RX_FILTER 0x08
391 #define XL_W5_RX_EARLYTHRESH 0x06
392 #define XL_W5_TX_AVAILTHRESH 0x02
393 #define XL_W5_TX_STARTTHRESH 0x00
398 #define XL_RXFILTER_INDIVIDUAL 0x01
399 #define XL_RXFILTER_ALLMULTI 0x02
400 #define XL_RXFILTER_BROADCAST 0x04
401 #define XL_RXFILTER_ALLFRAMES 0x08
402 #define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */
407 #define XL_W6_TX_BYTES_OK 0x0C
408 #define XL_W6_RX_BYTES_OK 0x0A
409 #define XL_W6_UPPER_FRAMES_OK 0x09
410 #define XL_W6_DEFERRED 0x08
411 #define XL_W6_RX_OK 0x07
412 #define XL_W6_TX_OK 0x06
413 #define XL_W6_RX_OVERRUN 0x05
414 #define XL_W6_COL_LATE 0x04
415 #define XL_W6_COL_SINGLE 0x03
416 #define XL_W6_COL_MULTIPLE 0x02
417 #define XL_W6_SQE_ERRORS 0x01
418 #define XL_W6_CARRIER_LOST 0x00
423 #define XL_W7_BM_ADDR 0x00
424 #define XL_W7_BM_LEN 0x06
425 #define XL_W7_BM_STATUS 0x0B
426 #define XL_W7_BM_TIMEr 0x0A
427 #define XL_W7_BM_PME 0x0C
429 #define XL_BM_PME_WAKE 0x0001
430 #define XL_BM_PME_MAGIC 0x0002
431 #define XL_BM_PME_LINKCHG 0x0004
432 #define XL_BM_PME_WAKETIMER 0x0008
436 #define XL_BM_PKTSTAT 0x20
437 #define XL_BM_DOWNLISTPTR 0x24
438 #define XL_BM_FRAGADDR 0x28
439 #define XL_BM_FRAGLEN 0x2C
440 #define XL_BM_TXFREETHRESH 0x2F
441 #define XL_BM_UPPKTSTAT 0x30
442 #define XL_BM_UPLISTPTR 0x38
444 #define XL_LAST_FRAG 0x80000000
459 * For the TX lists, bits 0 to 12 of the status word indicate
469 u_int32_t xl_next; /* final entry has 0 nextptr */
475 u_int32_t xl_next; /* final entry has 0 nextptr */
525 #define XL_RXSTAT_LENMASK 0x00001FFF
526 #define XL_RXSTAT_UP_ERROR 0x00004000
527 #define XL_RXSTAT_UP_CMPLT 0x00008000
528 #define XL_RXSTAT_UP_OVERRUN 0x00010000
529 #define XL_RXSTAT_RUNT 0x00020000
530 #define XL_RXSTAT_ALIGN 0x00040000
531 #define XL_RXSTAT_CRC 0x00080000
532 #define XL_RXSTAT_OVERSIZE 0x00100000
533 #define XL_RXSTAT_DRIBBLE 0x00800000
534 #define XL_RXSTAT_UP_OFLOW 0x01000000
535 #define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */
536 #define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */
537 #define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */
538 #define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */
539 #define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */
540 #define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */
541 #define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */
543 #define XL_TXSTAT_LENMASK 0x00001FFF
544 #define XL_TXSTAT_CRCDIS 0x00002000
545 #define XL_TXSTAT_TX_INTR 0x00008000
546 #define XL_TXSTAT_DL_COMPLETE 0x00010000
547 #define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */
548 #define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */
549 #define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */
550 #define XL_TXSTAT_RND_DEFEAT 0x10000000 /* 3c905B only */
551 #define XL_TXSTAT_EMPTY 0x20000000 /* 3c905B only */
552 #define XL_TXSTAT_DL_INTR 0x80000000
554 #define XL_CAPABILITY_BM 0x20
574 #define XL_FLAG_FUNCREG 0x0001
575 #define XL_FLAG_PHYOK 0x0002
576 #define XL_FLAG_EEPROM_OFFSET_30 0x0004
577 #define XL_FLAG_WEIRDRESET 0x0008
578 #define XL_FLAG_8BITROM 0x0010
579 #define XL_FLAG_INVERT_LED_PWR 0x0020
580 #define XL_FLAG_INVERT_MII_PWR 0x0040
581 #define XL_FLAG_NO_XCVR_PWR 0x0080
582 #define XL_FLAG_USE_MMIO 0x0100
583 #define XL_FLAG_NO_MMIO 0x0200
584 #define XL_FLAG_WOL 0x0400
586 #define XL_NO_XCVR_PWR_MAGICBITS 0x0900
628 ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok
631 ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok
675 } while (0)
684 #define TC_VENDORID 0x10B7
689 #define TC_DEVICEID_BOOMERANG_10BT 0x9000
690 #define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001
691 #define TC_DEVICEID_BOOMERANG_10_100BT 0x9050
692 #define TC_DEVICEID_BOOMERANG_100BT4 0x9051
693 #define TC_DEVICEID_KRAKATOA_10BT 0x9004
694 #define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005
695 #define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006
696 #define TC_DEVICEID_CYCLONE_10FL 0x900A
697 #define TC_DEVICEID_HURRICANE_10_100BT 0x9055
698 #define TC_DEVICEID_CYCLONE_10_100BT4 0x9056
699 #define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058
700 #define TC_DEVICEID_CYCLONE_10_100FX 0x905A
701 #define TC_DEVICEID_TORNADO_10_100BT 0x9200
702 #define TC_DEVICEID_TORNADO_10_100BT_920B 0x9201
703 #define TC_DEVICEID_TORNADO_10_100BT_920B_WNM 0x9202
704 #define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800
705 #define TC_DEVICEID_TORNADO_10_100BT_SERV 0x9805
706 #define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646
707 #define TC_DEVICEID_TORNADO_HOMECONNECT 0x4500
708 #define TC_DEVICEID_HURRICANE_555 0x5055
709 #define TC_DEVICEID_HURRICANE_556 0x6055
710 #define TC_DEVICEID_HURRICANE_556B 0x6056
711 #define TC_DEVICEID_HURRICANE_575A 0x5057
712 #define TC_DEVICEID_HURRICANE_575B 0x5157
713 #define TC_DEVICEID_HURRICANE_575C 0x5257
714 #define TC_DEVICEID_HURRICANE_656 0x6560
715 #define TC_DEVICEID_HURRICANE_656B 0x6562
716 #define TC_DEVICEID_TORNADO_656C 0x6564
723 #define XL_PCI_VENDOR_ID 0x00
724 #define XL_PCI_DEVICE_ID 0x02
725 #define XL_PCI_COMMAND 0x04
726 #define XL_PCI_STATUS 0x06
727 #define XL_PCI_CLASSCODE 0x09
728 #define XL_PCI_LATENCY_TIMER 0x0D
729 #define XL_PCI_HEADER_TYPE 0x0E
730 #define XL_PCI_LOIO 0x10
731 #define XL_PCI_LOMEM 0x14
732 #define XL_PCI_FUNCMEM 0x18
733 #define XL_PCI_BIOSROM 0x30
734 #define XL_PCI_INTLINE 0x3C
735 #define XL_PCI_INTPIN 0x3D
736 #define XL_PCI_MINGNT 0x3E
737 #define XL_PCI_MINLAT 0x0F
738 #define XL_PCI_RESETOPT 0x48
739 #define XL_PCI_EEPROM_DATA 0x4C
742 #define XL_PCI_CAPID 0xDC /* 8 bits */
743 #define XL_PCI_NEXTPTR 0xDD /* 8 bits */
744 #define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */
745 #define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
747 #define XL_PSTATE_MASK 0x0003
748 #define XL_PSTATE_D0 0x0000
749 #define XL_PSTATE_D1 0x0002
750 #define XL_PSTATE_D2 0x0002
751 #define XL_PSTATE_D3 0x0003
752 #define XL_PME_EN 0x0010
753 #define XL_PME_STATUS 0x8000