Lines Matching +full:0 +full:x04000

36 #define	XAE_RAF		0x00000 /* Reset and Address Filter RW */
37 #define	XAE_TPF		0x00004 /* Transmit Pause Frame RW */
38 #define	XAE_IFGP	0x00008 /* Transmit Inter Frame Gap Adjustment RW */
39 #define	XAE_IS		0x0000C /* Interrupt Status register RW */
40 #define	XAE_IP		0x00010 /* Interrupt Pending register RO */
41 #define	XAE_IE		0x00014 /* Interrupt Enable register RW */
42 #define	XAE_TTAG	0x00018 /* Transmit VLAN Tag RW */
43 #define	XAE_RTAG	0x0001C /* Receive VLAN Tag  RW */
44 #define	XAE_UAWL	0x00020 /* Unicast Address Word Lower RW */
45 #define	XAE_UAWU	0x00024 /* Unicast Address Word Upper RW */
46 #define	XAE_TPID0	0x00028 /* VLAN TPID Word 0 RW */
47 #define	XAE_TPID1	0x0002C /* VLAN TPID Word 1 RW */
48 #define	XAE_PPST	0x00030 /* PCS PMA Status register RO */
49 #define	XAE_STATCNT(n)	(0x00200 + 0x8 * (n)) /* Statistics Counters RO */
50 #define	XAE_RCW0	0x00400 /* Receive Configuration Word 0 Register RW */
51 #define	XAE_RCW1	0x00404 /* Receive Configuration Word 1 Register RW */
53 #define	XAE_TC		0x00408 /* Transmitter Configuration register RW */
55 #define	XAE_FCC		0x0040C /* Flow Control Configuration register RW */
57 #define	XAE_SPEED	0x00410 /* MAC Speed Configuration Word RW */
59 #define	 SPEED_10	(0 << SPEED_CONF_S)
62 #define	XAE_RX_MAXFRAME	0x00414 /* RX Max Frame Configuration RW */
63 #define	XAE_TX_MAXFRAME	0x00418 /* TX Max Frame Configuration RW */
64 #define	XAE_TX_TIMESTMP	0x0041C /* TX timestamp adjust control register RW */
65 #define	XAE_IDENT	0x004F8 /* Identification register RO */
66 #define	XAE_ABILITY	0x004FC /* Ability register RO */
67 #define	XAE_MDIO_SETUP	0x00500 /* MDIO Setup register RW */
69 #define	 MDIO_SETUP_CLK_DIV_S	0 /* Clock Divide */
70 #define	XAE_MDIO_CTRL	0x00504 /* MDIO Control RW */
72 #define	 MDIO_TX_REGAD_M	(0x1f << MDIO_TX_REGAD_S)
74 #define	 MDIO_TX_PHYAD_M	(0x1f << MDIO_TX_PHYAD_S)
76 #define	 MDIO_CTRL_TX_OP_M	(0x3 << MDIO_CTRL_TX_OP_S)
77 #define	 MDIO_CTRL_TX_OP_READ	(0x2 << MDIO_CTRL_TX_OP_S)
78 #define	 MDIO_CTRL_TX_OP_WRITE	(0x1 << MDIO_CTRL_TX_OP_S)
81 #define	XAE_MDIO_WRITE	0x00508 /* MDIO Write Data RW */
82 #define	XAE_MDIO_READ	0x0050C /* MDIO Read Data RO */
83 #define	XAE_INT_STATUS	0x00600 /* Interrupt Status Register RW */
84 #define	XAE_INT_PEND	0x00610 /* Interrupt Pending Register RO */
85 #define	XAE_INT_ENABLE	0x00620 /* Interrupt Enable Register RW */
86 #define	XAE_INT_CLEAR	0x00630 /* Interrupt Clear Register RW */
87 #define	XAE_UAW0	0x00700 /* Unicast Address Word 0 register (UAW0) RW */
88 #define	XAE_UAW1	0x00704 /* Unicast Address Word 1 register (UAW1) RW */
89 #define	XAE_FFC		0x00708 /* Frame Filter Control RW */
91 #define	XAE_FFV(n)	(0x00710 + 0x4 * (n)) /* Frame Filter Value RW */
92 #define	XAE_FFMV(n)	(0x00750 + 0x4 * (n)) /* Frame Filter Mask Value RW */
93 #define	XAE_TX_VLAN(n)	(0x04000 + 0x4 * (n)) /* Transmit VLAN Data Table RW */
94 #define	XAE_RX_VLAN(n)	(0x08000 + 0x4 * (n)) /* Receive VLAN Data Table RW */
95 #define	XAE_AVB(n)	(0x10000 + 0x4 * (n)) /* Ethernet AVB RW */
96 #define	XAE_MAT(n)	(0x20000 + 0x4 * (n)) /* Multicast Address Table RW */
101 #define	RX_BYTES			0