Lines Matching +full:0 +full:xe14
35 #define DSR 0x000 /* DMA Manager Status */
36 #define DPC 0x004 /* DMA Program Counter */
37 #define INTEN 0x020 /* Interrupt Enable */
38 #define INT_EVENT_RIS 0x024 /* Event-Interrupt Raw Status */
39 #define INTMIS 0x028 /* Interrupt Status */
40 #define INTCLR 0x02C /* Interrupt Clear */
41 #define FSRD 0x030 /* Fault Status DMA Manager */
42 #define FSRC 0x034 /* Fault Status DMA Channel */
43 #define FTRD 0x038 /* Fault Type DMA Manager */
44 #define FTR(n) (0x040 + 0x04 * (n)) /* Fault type for DMA channel n */
45 #define CSR(n) (0x100 + 0x08 * (n)) /* Channel status for DMA channel n */
46 #define CPC(n) (0x104 + 0x08 * (n)) /* Channel PC for DMA channel n */
47 #define SAR(n) (0x400 + 0x20 * (n)) /* Source address for DMA channel n */
48 #define DAR(n) (0x404 + 0x20 * (n)) /* Destination address for DMA channel n */
49 #define CCR(n) (0x408 + 0x20 * (n)) /* Channel control for DMA channel n */
51 #define CCR_DST_BURST_SIZE_1 (0 << CCR_DST_BURST_SIZE_S)
55 #define CCR_SRC_BURST_SIZE_1 (0 << CCR_SRC_BURST_SIZE_S)
59 #define CCR_SRC_INC (1 << 0)
62 #define LC0(n) (0x40C + 0x20 * (n)) /* Loop counter 0 for DMA channel n */
63 #define LC1(n) (0x410 + 0x20 * (n)) /* Loop counter 1 for DMA channel n */
65 #define DBGSTATUS 0xD00 /* Debug Status */
66 #define DBGCMD 0xD04 /* Debug Command */
67 #define DBGINST0 0xD08 /* Debug Instruction-0 */
68 #define DBGINST1 0xD0C /* Debug Instruction-1 */
69 #define CR0 0xE00 /* Configuration Register 0 */
70 #define CR1 0xE04 /* Configuration Register 1 */
71 #define CR2 0xE08 /* Configuration Register 2 */
72 #define CR3 0xE0C /* Configuration Register 3 */
73 #define CR4 0xE10 /* Configuration Register 4 */
74 #define CRD 0xE14 /* DMA Configuration */
75 #define WD 0xE80 /* Watchdog Register */
77 #define R_SAR 0
82 * 0xFE0- 0xFEC periph_id_n RO Configuration-dependent Peripheral Identification Registers
83 * 0xFF0- 0xFFC pcell_id_n RO Configuration-dependent Component Identification Registers
87 #define DMAADDH 0x54
88 #define DMAADNH 0x5c
89 #define DMAEND 0x00
90 #define DMAFLUSHP 0x35
91 #define DMAGO 0xa0
92 #define DMAKILL 0x01
93 #define DMALD 0x04
94 #define DMALDP 0x25
95 #define DMALP 0x20
96 #define DMALPEND 0x28
100 * #define DMALPFE 0
102 #define DMAMOV 0xbc
103 #define DMANOP 0x18
104 #define DMARMB 0x12
105 #define DMASEV 0x34
106 #define DMAST 0x08
107 #define DMASTP 0x29
108 #define DMASTZ 0x0c
109 #define DMAWFE 0x36
110 #define DMAWFP 0x30
111 #define DMAWMB 0x13