Lines Matching +full:0 +full:x41c

43 #define WPI_RING_DMA_ALIGN	0x4000
51 #define WPI_HW_IF_CONFIG	0x000
52 #define WPI_INT			0x008
53 #define WPI_INT_MASK		0x00c
54 #define WPI_FH_INT		0x010
55 #define WPI_GPIO_IN		0x018
56 #define WPI_RESET		0x020
57 #define WPI_GP_CNTRL		0x024
58 #define WPI_EEPROM		0x02c
59 #define WPI_EEPROM_GP		0x030
60 #define WPI_GIO			0x03c
61 #define WPI_UCODE_GP1		0x054
62 #define WPI_UCODE_GP1_SET	0x058
63 #define WPI_UCODE_GP1_CLR	0x05c
64 #define WPI_UCODE_GP2		0x060
65 #define WPI_GIO_CHICKEN		0x100
66 #define WPI_ANA_PLL		0x20c
67 #define WPI_DBG_HPET_MEM	0x240
68 #define WPI_MEM_RADDR		0x40c
69 #define WPI_MEM_WADDR		0x410
70 #define WPI_MEM_WDATA		0x418
71 #define WPI_MEM_RDATA		0x41c
72 #define WPI_PRPH_WADDR		0x444
73 #define WPI_PRPH_RADDR		0x448
74 #define WPI_PRPH_WDATA		0x44c
75 #define WPI_PRPH_RDATA		0x450
76 #define WPI_HBUS_TARG_WRPTR	0x460
81 #define WPI_FH_CBBC_CTRL(qid)	(0x940 + (qid) * 8)
82 #define WPI_FH_CBBC_BASE(qid)	(0x944 + (qid) * 8)
83 #define WPI_FH_RX_CONFIG	0xc00
84 #define WPI_FH_RX_BASE		0xc04
85 #define WPI_FH_RX_WPTR		0xc20
86 #define WPI_FH_RX_RPTR_ADDR	0xc24
87 #define WPI_FH_RSSR_TBL		0xcc0
88 #define WPI_FH_RX_STATUS	0xcc4
89 #define WPI_FH_TX_CONFIG(qid)	(0xd00 + (qid) * 32)
90 #define WPI_FH_TX_BASE		0xe80
91 #define WPI_FH_MSG_CONFIG	0xe88
92 #define WPI_FH_TX_STATUS	0xe90
97 #define WPI_ALM_SCHED_MODE		0x2e00
98 #define WPI_ALM_SCHED_ARASTAT		0x2e04
99 #define WPI_ALM_SCHED_TXFACT		0x2e10
100 #define WPI_ALM_SCHED_TXF4MF		0x2e14
101 #define WPI_ALM_SCHED_TXF5MF		0x2e20
102 #define WPI_ALM_SCHED_SBYPASS_MODE1	0x2e2c
103 #define WPI_ALM_SCHED_SBYPASS_MODE2	0x2e30
104 #define WPI_APMG_CLK_CTRL		0x3000
105 #define WPI_APMG_CLK_EN			0x3004
106 #define WPI_APMG_CLK_DIS		0x3008
107 #define WPI_APMG_PS			0x300c
108 #define WPI_APMG_PCI_STT		0x3010
109 #define WPI_APMG_RFKILL			0x3014
110 #define WPI_BSM_WR_CTRL			0x3400
111 #define WPI_BSM_WR_MEM_SRC		0x3404
112 #define WPI_BSM_WR_MEM_DST		0x3408
113 #define WPI_BSM_WR_DWCOUNT		0x340c
114 #define WPI_BSM_DRAM_TEXT_ADDR		0x3490
115 #define WPI_BSM_DRAM_TEXT_SIZE		0x3494
116 #define WPI_BSM_DRAM_DATA_ADDR		0x3498
117 #define WPI_BSM_DRAM_DATA_SIZE		0x349c
118 #define WPI_BSM_SRAM_BASE		0x3800
131 #define WPI_FW_TEXT_BASE	0x00000000
132 #define WPI_FW_DATA_BASE	0x00800000
138 #define WPI_RESET_NEVO			(1 << 0)
144 #define WPI_GP_CNTRL_MAC_ACCESS_ENA	(1 <<  0)
145 #define WPI_GP_CNTRL_MAC_CLOCK_READY	(1 <<  0)
173 #define WPI_UCODE_GP1_MAC_SLEEP		(1 << 0)
185 #define WPI_INT_ALIVE		(1  <<  0)
204 	(WPI_FH_INT_RX_CHNL(0) |	\
214 #define WPI_EEPROM_READ_VALID	(1 << 0)
217 #define WPI_EEPROM_VERSION	0x00000007
218 #define WPI_EEPROM_GP_IF_OWNER	0x00000180
256 #define WPI_TX_STATUS_SUCCESS			0x01
257 #define WPI_TX_STATUS_DIRECT_DONE		0x02
258 #define WPI_TX_STATUS_FAIL			0x80
259 #define WPI_TX_STATUS_FAIL_SHORT_LIMIT		0x82
260 #define WPI_TX_STATUS_FAIL_LONG_LIMIT		0x83
261 #define WPI_TX_STATUS_FAIL_FIFO_UNDERRUN	0x84
262 #define WPI_TX_STATUS_FAIL_MGMNT_ABORT		0x85
263 #define WPI_TX_STATUS_FAIL_NEXT_FRAG		0x86
264 #define WPI_TX_STATUS_FAIL_LIFE_EXPIRE		0x87
265 #define WPI_TX_STATUS_FAIL_NODE_PS		0x88
266 #define WPI_TX_STATUS_FAIL_ABORTED		0x89
267 #define WPI_TX_STATUS_FAIL_BT_RETRY		0x8a
268 #define WPI_TX_STATUS_FAIL_NODE_INVALID		0x8b
269 #define WPI_TX_STATUS_FAIL_FRAG_DROPPED		0x8c
270 #define WPI_TX_STATUS_FAIL_TID_DISABLE		0x8d
271 #define WPI_TX_STATUS_FAIL_FRAME_FLUSHED	0x8e
272 #define WPI_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL	0x8f
273 #define WPI_TX_STATUS_FAIL_TX_LOCKED		0x90
274 #define WPI_TX_STATUS_FAIL_NO_BEACON_ON_RADAR	0x91
298 #define WPI_RX_DESC_QID_MSK		0x07
299 #define WPI_UNSOLICITED_RX_NOTIF	0x80
326 #define WPI_RX_NO_CRC_ERR	(1 << 0)
384 #define WPI_RXON_24GHZ		(1 <<  0)
396 #define WPI_FILTER_PROMISC	(1 << 0)
420 #define WPI_EDCA_UPDATE	(1 << 0)
444 #define WPI_NODE_UPDATE		(1 << 0)
450 #define WPI_ID_BSS		0
457 #define WPI_FLAG_KEY_SET	(1 << 0)
523 #define WPI_LIFETIME_INFINITE	0xffffffff
562 #define WPI_MRR_CTL	0
590 #define WPI_PS_ALLOW_SLEEP	(1 << 0)
635 #define WPI_CHAN_ACTIVE		(1 << 0)
646 #define WPI_SCAN_CRC_TH_NEVER		htole16(0xffff)
664 #define WPI_BAND_5GHZ	0
682 #define WPI_BT_COEX_DISABLE	0
838 #define WPI_EEPROM_MAC		0x015
839 #define WPI_EEPROM_REVISION	0x035
840 #define WPI_EEPROM_SKU_CAP	0x045
841 #define WPI_EEPROM_TYPE		0x04a
842 #define WPI_EEPROM_DOMAIN	0x060
843 #define WPI_EEPROM_BAND1	0x063
844 #define WPI_EEPROM_BAND2	0x072
845 #define WPI_EEPROM_BAND3	0x080
846 #define WPI_EEPROM_BAND4	0x08d
847 #define WPI_EEPROM_BAND5	0x099
848 #define WPI_EEPROM_POWER_GRP	0x100
852 #define WPI_EEPROM_CHAN_VALID	(1 << 0)
898 #define WPI_RIDX_OFDM6	 0
909 	0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3,
921 	0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb,
922 	0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3,
923 	0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb,
924 	0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b,
925 	0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3,
926 	0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63,
927 	0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03,
928 	0x03
932 	0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b,
933 	0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b,
934 	0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33,
935 	0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b,
936 	0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b,
937 	0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63,
938 	0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23,
939 	0x03
947 	0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c,
948 	0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b,
949 	0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d,
950 	0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74,
951 	0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71,
952 	0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f,
953 	0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66,
954 	0x5f
958 	0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b,
959 	0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62,
960 	0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f,
961 	0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78,
962 	0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63,
963 	0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78,
964 	0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63,
965 	0x78
981 	{   0,   0, {  0,  0,  0,  0,  0 }, 0 },	/* CAM */
982 	{ 200, 500, {  1,  2,  3,  4,  4 }, 0 },	/* PS level 1 */
983 	{ 200, 300, {  2,  4,  6,  7,  7 }, 0 },	/* PS level 2 */
984 	{  50, 100, {  2,  6,  9,  9, 10 }, 0 },	/* PS level 3 */
990 	{   0,   0, {  0,  0,  0,  0,  0 }, 0 },	/* CAM */
991 	{ 200, 500, {  1,  2,  3,  4, -1 }, 0 },	/* PS level 1 */
992 	{ 200, 300, {  2,  4,  6,  7, -1 }, 0 },	/* PS level 2 */
993 	{  50, 100, {  2,  6,  9,  9, -1 }, 0 },	/* PS level 3 */
994 	{  50,  25, {  2,  7,  9,  9, -1 }, 0 },	/* PS level 4 */
995 	{  25,  25, {  4,  7, 10, 10, -1 }, 0 }		/* PS level 5 */
1027 	bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz,	\
1031 	bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz,	\