Lines Matching +full:0 +full:x0040
36 #define VENDORID_RDC 0x17F3
41 #define DEVICEID_RDC_R6040 0x6040 /* PMX-1000 */
43 /* MAC control register 0 */
44 #define VTE_MCR0 0x00
45 #define MCR0_ACCPT_ERR 0x0001
46 #define MCR0_RX_ENB 0x0002
47 #define MCR0_ACCPT_RUNT 0x0004
48 #define MCR0_ACCPT_LONG_PKT 0x0008
49 #define MCR0_ACCPT_DRIBBLE 0x0010
50 #define MCR0_PROMISC 0x0020
51 #define MCR0_BROADCAST_DIS 0x0040
52 #define MCR0_RX_EARLY_INTR 0x0080
53 #define MCR0_MULTICAST 0x0100
54 #define MCR0_FC_ENB 0x0200
55 #define MCR0_TX_ENB 0x1000
56 #define MCR0_TX_EARLY_INTR 0x4000
57 #define MCR0_FULL_DUPLEX 0x8000
60 #define VTE_MCR1 0x04
61 #define MCR1_MAC_RESET 0x0001
62 #define MCR1_MAC_LOOPBACK 0x0002
63 #define MCR1_EXCESS_COL_RETRANS_DIS 0x0004
64 #define MCR1_AUTO_CHG_DUPLEX 0x0008
65 #define MCR1_PKT_LENGTH_1518 0x0010
66 #define MCR1_PKT_LENGTH_1522 0x0020
67 #define MCR1_PKT_LENGTH_1534 0x0030
68 #define MCR1_PKT_LENGTH_1537 0x0000
69 #define MCR1_EARLY_INTR_THRESH_1129 0x0000
70 #define MCR1_EARLY_INTR_THRESH_1257 0x0040
71 #define MCR1_EARLY_INTR_THRESH_1385 0x0080
72 #define MCR1_EARLY_INTR_THRESH_1513 0x00C0
73 #define MCR1_EXCESS_COL_RETRY_16 0x0000
74 #define MCR1_EXCESS_COL_RETRY_32 0x0100
75 #define MCR1_FC_ACTIVE 0x0200
76 #define MCR1_RX_DESC_HASH_IDX 0x4000
77 #define MCR1_RX_UNICAST_HASH 0x8000
79 #define MCR1_PKT_LENGTH_MASK 0x0030
80 #define MCR1_EARLY_INTR_THRESH_MASK 0x00C0
83 #define VTE_MBCR 0x08
84 #define MBCR_FIFO_XFER_LENGTH_4 0x0000
85 #define MBCR_FIFO_XFER_LENGTH_8 0x0001
86 #define MBCR_FIFO_XFER_LENGTH_16 0x0002
87 #define MBCR_FIFO_XFER_LENGTH_32 0x0003
88 #define MBCR_TX_FIFO_THRESH_16 0x0000
89 #define MBCR_TX_FIFO_THRESH_32 0x0004
90 #define MBCR_TX_FIFO_THRESH_64 0x0008
91 #define MBCR_TX_FIFO_THRESH_96 0x000C
92 #define MBCR_RX_FIFO_THRESH_8 0x0000
93 #define MBCR_RX_FIFO_THRESH_16 0x0010
94 #define MBCR_RX_FIFO_THRESH_32 0x0020
95 #define MBCR_RX_FIFO_THRESH_64 0x0030
96 #define MBCR_SDRAM_BUS_REQ_TIMER_MASK 0x1F00
98 #define MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT 0x1F00
101 #define VTE_MTICR 0x0C
102 #define MTICR_TX_TIMER_MASK 0x001F
103 #define MTICR_TX_BUNDLE_MASK 0x0F00
104 #define VTE_IM_TX_TIMER_DEFAULT 0x7F
107 #define VTE_IM_TIMER_MIN 0
109 #define VTE_IM_TIMER_MASK 0x001F
110 #define VTE_IM_TIMER_SHIFT 0
116 #define VTE_MRICR 0x10
117 #define MRICR_RX_TIMER_MASK 0x001F
118 #define MRICR_RX_BUNDLE_MASK 0x0F00
119 #define VTE_IM_RX_TIMER_DEFAULT 0x7F
123 #define VTE_TX_POLL 0x14
124 #define TX_POLL_START 0x0001
127 #define VTE_MRBSR 0x18
128 #define VTE_MRBSR_SIZE_MASK 0x03FF
131 #define VTE_MRDCR 0x1A
132 #define VTE_MRDCR_RESIDUE_MASK 0x00FF
133 #define VTE_MRDCR_RX_PAUSE_THRESH_MASK 0xFF00
137 #define VTE_MLSR 0x1C
138 #define MLSR_MULTICAST 0x0001
139 #define MLSR_BROADCAST 0x0002
140 #define MLSR_CRC_ERR 0x0004
141 #define MLSR_RUNT 0x0008
142 #define MLSR_LONG_PKT 0x0010
143 #define MLSR_TRUNC 0x0020
144 #define MLSR_DRIBBLE 0x0040
145 #define MLSR_PHY_ERR 0x0080
146 #define MLSR_TX_FIFO_UNDERRUN 0x0200
147 #define MLSR_RX_DESC_UNAVAIL 0x0400
148 #define MLSR_TX_EXCESS_COL 0x2000
149 #define MLSR_TX_LATE_COL 0x4000
150 #define MLSR_RX_FIFO_OVERRUN 0x8000
153 #define VTE_MMDIO 0x20
154 #define MMDIO_REG_ADDR_MASK 0x001F
155 #define MMDIO_PHY_ADDR_MASK 0x1F00
156 #define MMDIO_READ 0x2000
157 #define MMDIO_WRITE 0x4000
158 #define MMDIO_REG_ADDR_SHIFT 0
162 #define VTE_MMRD 0x24
163 #define MMRD_DATA_MASK 0xFFFF
166 #define VTE_MMWD 0x28
167 #define MMWD_DATA_MASK 0xFFFF
169 /* MAC TX descriptor start address 0 */
170 #define VTE_MTDSA0 0x2C
173 #define VTE_MTDSA1 0x30
175 /* MAC RX descriptor start address 0 */
176 #define VTE_MRDSA0 0x34
179 #define VTE_MRDSA1 0x38
182 #define VTE_MISR 0x3C
183 #define MISR_RX_DONE 0x0001
184 #define MISR_RX_DESC_UNAVAIL 0x0002
185 #define MISR_RX_FIFO_FULL 0x0004
186 #define MISR_RX_EARLY_INTR 0x0008
187 #define MISR_TX_DONE 0x0010
188 #define MISR_TX_EARLY_INTR 0x0080
189 #define MISR_EVENT_CNT_OFLOW 0x0100
190 #define MISR_PHY_MEDIA_CHG 0x0200
193 #define VTE_MIER 0x40
200 #define VTE_MECISR 0x44
201 #define MECISR_EC_RX_DONE 0x0001
202 #define MECISR_EC_MULTICAST 0x0002
203 #define MECISR_EC_BROADCAST 0x0004
204 #define MECISR_EC_CRC_ERR 0x0008
205 #define MECISR_EC_RUNT 0x0010
206 #define MESCIR_EC_LONG_PKT 0x0020
207 #define MESCIR_EC_RX_DESC_UNAVAIL 0x0080
208 #define MESCIR_EC_RX_FIFO_FULL 0x0100
209 #define MESCIR_EC_TX_DONE 0x0200
210 #define MESCIR_EC_LATE_COL 0x0400
211 #define MESCIR_EC_TX_UNDERRUN 0x0800
214 #define VTE_MECIER 0x48
221 #define VTE_CNT_RX_DONE 0x50
223 #define VTE_CNT_MECNT0 0x52
225 #define VTE_CNT_MECNT1 0x54
227 #define VTE_CNT_MECNT2 0x56
229 #define VTE_CNT_MECNT3 0x58
231 #define VTE_CNT_TX_DONE 0x5A
233 #define VTE_CNT_MECNT4 0x5C
235 #define VTE_CNT_PAUSE 0x5E
238 #define VTE_MAR0 0x60
239 #define VTE_MAR1 0x62
240 #define VTE_MAR2 0x64
241 #define VTE_MAR3 0x66
244 #define VTE_MID0L 0x68
245 #define VTE_MID0M 0x6A
246 #define VTE_MID0H 0x6C
247 #define VTE_MID1L 0x70
248 #define VTE_MID1M 0x72
249 #define VTE_MID1H 0x74
250 #define VTE_MID2L 0x78
251 #define VTE_MID2M 0x7A
252 #define VTE_MID2H 0x7C
253 #define VTE_MID3L 0x80
254 #define VTE_MID3M 0x82
255 #define VTE_MID3H 0x84
261 #define VTE_MPSCCR 0x88
262 #define MPSCCR_TIMER_DIVIDER_MASK 0x0007
263 #define MPSCCR_PHY_ADDR_MASK 0x1F00
264 #define MPSCCR_PHY_STS_CHG_ENB 0x8000
268 #define VTE_MPSR 0x8A
269 #define MPSR_LINK_UP 0x0001
270 #define MPSR_SPEED_100 0x0002
271 #define MPSR_FULL_DUPLEX 0x0004
274 #define VTE_MACSM 0xAC
277 #define VTE_MDCSC 0xB6
278 #define MDCSC_DEFAULT 0x0030
281 #define VTE_MACID_REV 0xBC
282 #define VTE_MACID_REV_MASK 0x00FF
283 #define VTE_MACID_MASK 0xFF00
284 #define VTE_MACID_REV_SHIFT 0
288 #define VTE_MACID 0xBE
307 #define VTE_DRST_MID_MASK 0x0003
308 #define VTE_DRST_MID_HIT 0x0004
309 #define VTE_DRST_MULTICAST_HIT 0x0008
310 #define VTE_DRST_MULTICAST 0x0010
311 #define VTE_DRST_BROADCAST 0x0020
312 #define VTE_DRST_CRC_ERR 0x0040
313 #define VTE_DRST_RUNT 0x0080
314 #define VTE_DRST_LONG 0x0100
315 #define VTE_DRST_TRUNC 0x0200
316 #define VTE_DRST_DRIBBLE 0x0400
317 #define VTE_DRST_PHY_ERR 0x0800
318 #define VTE_DRST_RX_OK 0x4000
319 #define VTE_DRST_RX_OWN 0x8000
321 #define VTE_RX_LEN(x) ((x) & 0x7FF)
323 #define VTE_RX_HIDX(x) ((x) & 0x3F)
337 #define VTE_DTST_EXCESS_COL 0x0010
338 #define VTE_DTST_LATE_COL 0x0020
339 #define VTE_DTST_UNDERRUN 0x0040
340 #define VTE_DTST_NO_CRC 0x2000
341 #define VTE_DTST_TX_OK 0x4000
342 #define VTE_DTST_TX_OWN 0x8000
344 #define VTE_TX_LEN(x) ((x) & 0x7FF)