Lines Matching +full:0 +full:x610

43 #define	BGX_CMRX_CFG			0x00
47 #define BGX_CMR_GLOBAL_CFG 0x08
49 #define BGX_CMRX_RX_ID_MAP 0x60
50 #define BGX_CMRX_RX_STAT0 0x70
51 #define BGX_CMRX_RX_STAT1 0x78
52 #define BGX_CMRX_RX_STAT2 0x80
53 #define BGX_CMRX_RX_STAT3 0x88
54 #define BGX_CMRX_RX_STAT4 0x90
55 #define BGX_CMRX_RX_STAT5 0x98
56 #define BGX_CMRX_RX_STAT6 0xA0
57 #define BGX_CMRX_RX_STAT7 0xA8
58 #define BGX_CMRX_RX_STAT8 0xB0
59 #define BGX_CMRX_RX_STAT9 0xB8
60 #define BGX_CMRX_RX_STAT10 0xC0
61 #define BGX_CMRX_RX_BP_DROP 0xC8
62 #define BGX_CMRX_RX_DMAC_CTL 0x0E8
63 #define BGX_CMR_RX_DMACX_CAM 0x200
67 #define BGX_CMR_RX_STREERING 0x300
69 #define BGX_CMR_CHAN_MSK_AND 0x450
70 #define BGX_CMR_BIST_STATUS 0x460
71 #define BGX_CMR_RX_LMACS 0x468
72 #define BGX_CMRX_TX_STAT0 0x600
73 #define BGX_CMRX_TX_STAT1 0x608
74 #define BGX_CMRX_TX_STAT2 0x610
75 #define BGX_CMRX_TX_STAT3 0x618
76 #define BGX_CMRX_TX_STAT4 0x620
77 #define BGX_CMRX_TX_STAT5 0x628
78 #define BGX_CMRX_TX_STAT6 0x630
79 #define BGX_CMRX_TX_STAT7 0x638
80 #define BGX_CMRX_TX_STAT8 0x640
81 #define BGX_CMRX_TX_STAT9 0x648
82 #define BGX_CMRX_TX_STAT10 0x650
83 #define BGX_CMRX_TX_STAT11 0x658
84 #define BGX_CMRX_TX_STAT12 0x660
85 #define BGX_CMRX_TX_STAT13 0x668
86 #define BGX_CMRX_TX_STAT14 0x670
87 #define BGX_CMRX_TX_STAT15 0x678
88 #define BGX_CMRX_TX_STAT16 0x680
89 #define BGX_CMRX_TX_STAT17 0x688
90 #define BGX_CMR_TX_LMACS 0x1000
92 #define BGX_SPUX_CONTROL1 0x10000
96 #define BGX_SPUX_STATUS1 0x10008
98 #define BGX_SPUX_STATUS2 0x10020
100 #define BGX_SPUX_BX_STATUS 0x10028
102 #define BGX_SPUX_BR_STATUS1 0x10030
103 #define SPU_BR_STATUS_BLK_LOCK (1UL << 0)
105 #define BGX_SPUX_BR_PMD_CRTL 0x10068
107 #define BGX_SPUX_BR_PMD_LP_CUP 0x10078
108 #define BGX_SPUX_BR_PMD_LD_CUP 0x10088
109 #define BGX_SPUX_BR_PMD_LD_REP 0x10090
110 #define BGX_SPUX_FEC_CONTROL 0x100A0
111 #define SPU_FEC_CTL_FEC_EN (1UL << 0)
113 #define BGX_SPUX_AN_CONTROL 0x100C8
116 #define BGX_SPUX_AN_ADV 0x100D8
117 #define BGX_SPUX_MISC_CONTROL 0x10218
120 #define BGX_SPUX_INT 0x10220 /* +(0..3) << 20 */
121 #define BGX_SPUX_INT_W1S 0x10228
122 #define BGX_SPUX_INT_ENA_W1C 0x10230
123 #define BGX_SPUX_INT_ENA_W1S 0x10238
124 #define BGX_SPU_DBG_CONTROL 0x10300
128 #define BGX_SMUX_RX_INT 0x20000
129 #define BGX_SMUX_RX_JABBER 0x20030
130 #define BGX_SMUX_RX_CTL 0x20048
131 #define SMU_RX_CTL_STATUS (3UL << 0)
132 #define BGX_SMUX_TX_APPEND 0x20100
134 #define BGX_SMUX_TX_MIN_PKT 0x20118
135 #define BGX_SMUX_TX_INT 0x20140
136 #define BGX_SMUX_TX_CTL 0x20178
137 #define SMU_TX_CTL_DIC_EN (1UL << 0)
140 #define BGX_SMUX_TX_THRESH 0x20180
141 #define BGX_SMUX_CTL 0x20200
142 #define SMU_CTL_RX_IDLE (1UL << 0)
145 #define BGX_GMP_PCS_MRX_CTL 0x30000
151 #define BGX_GMP_PCS_MRX_STATUS 0x30008
153 #define BGX_GMP_PCS_ANX_AN_RESULTS 0x30020
154 #define BGX_GMP_PCS_SGM_AN_ADV 0x30068
155 #define BGX_GMP_PCS_MISCX_CTL 0x30078
157 #define PCS_MISC_CTL_SAMP_PT_MASK 0x7FUL
158 #define BGX_GMP_GMI_PRTX_CFG 0x38020
163 #define BGX_GMP_GMI_RXX_JABBER 0x38038
164 #define BGX_GMP_GMI_TXX_THRESH 0x38210
165 #define BGX_GMP_GMI_TXX_APPEND 0x38218
166 #define BGX_GMP_GMI_TXX_SLOT 0x38220
167 #define BGX_GMP_GMI_TXX_BURST 0x38228
168 #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240
169 #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300
171 #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */
172 #define BGX_MSIX_VEC_0_29_CTL 0x400008
173 #define BGX_MSIX_PBA_0 0x4F0000
180 #define CMRX_INT 0
190 #define LMAC_INTR_LINK_UP (1 << 0)
226 BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */