Lines Matching +full:- +full:1 +full:ul
8 * 1. Redistributions of source code must retain the above copyright
44 #define CMR_PKT_TX_EN (1UL << 13)
45 #define CMR_PKT_RX_EN (1UL << 14)
46 #define CMR_EN (1UL << 15)
48 #define CMR_GLOBAL_CFG_FCS_STRIP (1UL << 6)
64 #define RX_DMACX_CAM_EN (1UL << 48)
93 #define SPU_CTL_LOW_POWER (1UL << 11)
94 #define SPU_CTL_LOOPBACK (1UL << 14)
95 #define SPU_CTL_RESET (1UL << 15)
97 #define SPU_STATUS1_RCV_LNK (1UL << 2)
99 #define SPU_STATUS2_RCVFLT (1UL << 10)
101 #define SPU_BX_STATUS_RX_ALIGN (1UL << 12)
103 #define SPU_BR_STATUS_BLK_LOCK (1UL << 0)
104 #define SPU_BR_STATUS_RCV_LNK (1UL << 12)
106 #define SPU_PMD_CRTL_TRAIN_EN (1UL << 1)
111 #define SPU_FEC_CTL_FEC_EN (1UL << 0)
112 #define SPU_FEC_CTL_ERR_EN (1UL << 1)
114 #define SPU_AN_CTL_AN_EN (1UL << 12)
115 #define SPU_AN_CTL_XNP_EN (1UL << 13)
118 #define SPU_MISC_CTL_INTLV_RDISP (1UL << 10)
119 #define SPU_MISC_CTL_RX_DIS (1UL << 12)
125 #define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN (1UL << 18)
126 #define SPU_DBG_CTL_AN_NONCE_MCT_DIS (1UL << 29)
131 #define SMU_RX_CTL_STATUS (3UL << 0)
133 #define SMU_TX_APPEND_FCS_D (1UL << 2)
137 #define SMU_TX_CTL_DIC_EN (1UL << 0)
138 #define SMU_TX_CTL_UNI_EN (1UL << 1)
139 #define SMU_TX_CTL_LNK_STATUS (3UL << 4)
142 #define SMU_CTL_RX_IDLE (1UL << 0)
143 #define SMU_CTL_TX_IDLE (1UL << 1)
146 #define PCS_MRX_CTL_RST_AN (1UL << 9)
147 #define PCS_MRX_CTL_PWR_DN (1UL << 11)
148 #define PCS_MRX_CTL_AN_EN (1UL << 12)
149 #define PCS_MRX_CTL_LOOPBACK1 (1UL << 14)
150 #define PCS_MRX_CTL_RESET (1UL << 15)
152 #define PCS_MRX_STATUS_AN_CPT (1UL << 5)
156 #define PCS_MISC_CTL_GMX_ENO (1UL << 11)
159 #define GMI_PORT_CFG_SPEED (1UL << 1)
160 #define GMI_PORT_CFG_DUPLEX (1UL << 2)
161 #define GMI_PORT_CFG_SLOT_TIME (1UL << 3)
162 #define GMI_PORT_CFG_SPEED_MSB (1UL << 8)
175 /* MSI-X interrupts */
181 #define SPUX_INT 1
190 #define LMAC_INTR_LINK_UP (1 << 0)
191 #define LMAC_INTR_LINK_DOWN (1 << 1)
201 #define BCAST_ACCEPT 1
202 #define CAM_ACCEPT 1
223 #define BGX_IN_PROMISCUOUS_MODE 1
226 BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */
227 BGX_MODE_XAUI = 1, /* 4 lanes, 3.125 Gbaud */
228 BGX_MODE_DXAUI = 1, /* 4 lanes, 6.250 Gbaud */
230 BGX_MODE_XFI = 3, /* 1 lane, 10.3125 Gbaud */
232 BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */
238 QLM_MODE_XAUI_1X4, /* 1 XAUI or DXAUI, 4 lanes */
240 QLM_MODE_XFI_4X1, /* 4 XFI, 1 lane each */
241 QLM_MODE_XLAUI_1X4, /* 1 XLAUI, 4 lanes each */
242 QLM_MODE_10G_KR_4X1, /* 4 10GBASE-KR, 1 lane each */
243 QLM_MODE_40G_KR4_1X4, /* 1 40GBASE-KR4, 4 lanes each */