Lines Matching +full:tx +full:- +full:rx
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
54 #define VGE_RXCTL 0x06 /* RX control register */
55 #define VGE_TXCTL 0x07 /* TX control register */
81 #define VGE_TXHOSTERR 0x22 /* TX host error status */
82 #define VGE_RXHOSTERR 0x23 /* RX host error status */
86 #define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */
87 #define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */
88 #define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */
89 #define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */
90 #define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */
91 #define VGE_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */
92 #define VGE_TXQTIMER 0x3E /* TX queue timer pend register */
93 #define VGE_RXQTIMER 0x3F /* RX queue timer pend register */
94 #define VGE_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */
95 #define VGE_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */
96 #define VGE_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */
97 #define VGE_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */
98 #define VGE_RXDESCNUM 0x50 /* Size of RX desc ring */
99 #define VGE_TXDESCNUM 0x52 /* Size of TX desc ring */
100 #define VGE_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */
101 #define VGE_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */
102 #define VGE_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */
103 #define VGE_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */
104 #define VGE_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */
105 #define VGE_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */
119 #define VGE_SSTIMER 0x74 /* single-shot timer */
127 #define VGE_RXCFG 0x7E /* MAC RX config */
128 #define VGE_TXCFG 0x7F /* MAC TX config */
211 #define VGE_CR0_RX_ENABLE 0x04 /* turn on RX engine */
212 #define VGE_CR0_TX_ENABLE 0x08 /* turn on TX engine */
217 #define VGE_CR1_NOPOLL 0x08 /* disable RX/TX desc polling */
224 #define VGE_CR2_TXPAUSE_THRESH_LO 0x03 /* TX pause frame lo threshold */
225 #define VGE_CR2_TXPAUSE_THRESH_HI 0x0C /* TX pause frame hi threshold */
227 #define VGE_CR2_FDX_RXFLOWCTL_ENABLE 0x20 /* full duplex RX flow control */
228 #define VGE_CR2_FDX_TXFLOWCTL_ENABLE 0x40 /* full duplex TX flow control */
233 #define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */
246 #define VGE_INTCTL_RXINTSUP_DISABLE 0x20 /* disable RX int supression */
247 #define VGE_INTCTL_TXINTSUP_DISABLE 0x40 /* disable TX int supression */
257 #define VGE_TXHOSTERR_TDSTRUCT 0x01 /* bad TX desc structure */
260 #define VGE_TXHOSTERR_FIFOERR 0x08 /* TX FIFO DMA bus error */
264 #define VGE_RXHOSTERR_RDSTRUCT 0x01 /* bad RX desc structure */
267 #define VGE_RXHOSTERR_FIFOERR 0x08 /* RX FIFO DMA bus error */
271 #define VGE_ISR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */
272 #define VGE_ISR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */
273 #define VGE_ISR_RXOK 0x00000004 /* normal RX done */
275 #define VGE_ISR_TXOK0 0x00000010 /* TX complete on queue 0 */
276 #define VGE_ISR_TXOK1 0x00000020 /* TX complete on queue 1 */
277 #define VGE_ISR_TXOK2 0x00000040 /* TX complete on queue 2 */
278 #define VGE_ISR_TXOK3 0x00000080 /* TX complete on queue 3 */
279 #define VGE_ISR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */
280 #define VGE_ISR_RXPAUSE 0x00000800 /* pause frame RX'ed */
281 #define VGE_ISR_RXOFLOW 0x00001000 /* RX FIFO overflow */
282 #define VGE_ISR_RXNODESC 0x00002000 /* ran out of RX descriptors */
283 #define VGE_ISR_RXNODESC_WARN 0x00004000 /* running out of RX descs */
293 #define VGE_ISR_RXDMA_STALL 0x01000000 /* RX DMA stall */
294 #define VGE_ISR_TXDMA_STALL 0x02000000 /* TX DMA STALL */
309 #define VGE_IMR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */
310 #define VGE_IMR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */
311 #define VGE_IMR_RXOK 0x00000004 /* normal RX done */
313 #define VGE_IMR_TXOK0 0x00000010 /* TX complete on queue 0 */
314 #define VGE_IMR_TXOK1 0x00000020 /* TX complete on queue 1 */
315 #define VGE_IMR_TXOK2 0x00000040 /* TX complete on queue 2 */
316 #define VGE_IMR_TXOK3 0x00000080 /* TX complete on queue 3 */
317 #define VGE_IMR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */
318 #define VGE_IMR_RXPAUSE 0x00000800 /* pause frame RX'ed */
319 #define VGE_IMR_RXOFLOW 0x00001000 /* RX FIFO overflow */
320 #define VGE_IMR_RXNODESC 0x00002000 /* ran out of RX descriptors */
321 #define VGE_IMR_RXNODESC_WARN 0x00004000 /* running out of RX descs */
331 #define VGE_IMR_RXDMA_STALL 0x01000000 /* RX DMA stall */
332 #define VGE_IMR_TXDMA_STALL 0x02000000 /* TX DMA STALL */
338 /* TX descriptor queue control/status register */
340 #define VGE_TXQCSR_RUN0 0x0001 /* Enable TX queue 0 */
344 #define VGE_TXQCSR_RUN1 0x0010 /* Enable TX queue 1 */
348 #define VGE_TXQCSR_RUN2 0x0100 /* Enable TX queue 2 */
352 #define VGE_TXQCSR_RUN3 0x1000 /* Enable TX queue 3 */
357 /* RX descriptor queue control/status register */
359 #define VGE_RXQCSR_RUN 0x0001 /* Enable RX queue */
364 /* RX/TX queue empty interrupt delay timer register */
386 * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the
389 * - The behavior of the interrupt holdoff timer register at offset
391 * holdoff timer, the TX interrupt supression count or the
392 * RX interrupt supression count)
393 * - The behavior the WOL pattern programming registers at offset
431 #define VGE_PHYSTS_TXFLOWCAP 0x01 /* resolved TX flow control cap */
432 #define VGE_PHYSTS_RXFLOWCAP 0x02 /* resolved RX flow control cap */
456 #define VGE_CHIPCFG0_PACPI 0x01 /* pre-ACPI wakeup function */
485 #define VGE_DMACFG0_BURSTLEN 0x07 /* RX/TX DMA burst (in dwords) */
504 /* RX MAC config register */
508 #define VGE_RXCFG_FIFO_LOWAT 0x08 /* RX FIFO low watermark (7QW/15QW) */
509 #define VGE_RXCFG_FIFO_THR 0x30 /* RX FIFO threshold */
512 #define VGE_VTAG_OPT0 0x00 /* TX: no tag insertion
513 RX: rx all, no tag extraction */
515 #define VGE_VTAG_OPT1 0x02 /* TX: no tag insertion
516 RX: rx only tagged pkts, no
519 #define VGE_VTAG_OPT2 0x04 /* TX: perform tag insertion,
520 RX: rx all, extract tags */
522 #define VGE_VTAG_OPT3 0x06 /* TX: perform tag insertion,
523 RX: rx only tagged pkts,
531 /* TX MAC config register */
537 #define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */
538 #define VGE_TXCFG_NONBLK_THR 0x0C /* non-blocking threshold */
590 #define VGE_MIB_CNT (VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1)
665 * Each TX DMA descriptor has a control and status word, and 7
679 * Normally, the chip requires the driver to issue a TX poll command
680 * for every packet that gets put in the TX DMA queue. Sometimes though,
694 #define VGE_TDSTS_COLLCNT 0x0000000F /* TX collision count */
697 #define VGE_TDSTS_OWT 0x00000040 /* jumbo frame tx abort */
698 #define VGE_TDSTS_EXCESSCOLL 0x00000080 /* TX aborted, excess colls */
701 #define VGE_TDSTS_SHUTDOWN 0x00000400 /* shutdown during TX */
702 #define VGE_TDSTS_LINKFAIL 0x00001000 /* link fail during TX */
738 * Like the TX descriptor, the high bit in the buflen field in the
739 * RX descriptor has special meaning. This bit controls whether or
749 #define VGE_RDSTS_RLERR 0x00000010 /* RX length error */
751 #define VGE_RDSTS_SNTAG 0x00000040 /* RX'ed tagged SNAP pkt */
761 #define VGE_RDSTS_SHUTDOWN 0x40000000 /* shutdown during RX */