Lines Matching full:tx
55 #define VGE_TXCTL 0x07 /* TX control register */
81 #define VGE_TXHOSTERR 0x22 /* TX host error status */
86 #define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */
88 #define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */
92 #define VGE_TXQTIMER 0x3E /* TX queue timer pend register */
94 #define VGE_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */
95 #define VGE_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */
96 #define VGE_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */
97 #define VGE_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */
99 #define VGE_TXDESCNUM 0x52 /* Size of TX desc ring */
100 #define VGE_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */
101 #define VGE_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */
102 #define VGE_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */
103 #define VGE_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */
104 #define VGE_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */
128 #define VGE_TXCFG 0x7F /* MAC TX config */
212 #define VGE_CR0_TX_ENABLE 0x08 /* turn on TX engine */
217 #define VGE_CR1_NOPOLL 0x08 /* disable RX/TX desc polling */
224 #define VGE_CR2_TXPAUSE_THRESH_LO 0x03 /* TX pause frame lo threshold */
225 #define VGE_CR2_TXPAUSE_THRESH_HI 0x0C /* TX pause frame hi threshold */
228 #define VGE_CR2_FDX_TXFLOWCTL_ENABLE 0x40 /* full duplex TX flow control */
247 #define VGE_INTCTL_TXINTSUP_DISABLE 0x40 /* disable TX int supression */
257 #define VGE_TXHOSTERR_TDSTRUCT 0x01 /* bad TX desc structure */
260 #define VGE_TXHOSTERR_FIFOERR 0x08 /* TX FIFO DMA bus error */
272 #define VGE_ISR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */
275 #define VGE_ISR_TXOK0 0x00000010 /* TX complete on queue 0 */
276 #define VGE_ISR_TXOK1 0x00000020 /* TX complete on queue 1 */
277 #define VGE_ISR_TXOK2 0x00000040 /* TX complete on queue 2 */
278 #define VGE_ISR_TXOK3 0x00000080 /* TX complete on queue 3 */
294 #define VGE_ISR_TXDMA_STALL 0x02000000 /* TX DMA STALL */
310 #define VGE_IMR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */
313 #define VGE_IMR_TXOK0 0x00000010 /* TX complete on queue 0 */
314 #define VGE_IMR_TXOK1 0x00000020 /* TX complete on queue 1 */
315 #define VGE_IMR_TXOK2 0x00000040 /* TX complete on queue 2 */
316 #define VGE_IMR_TXOK3 0x00000080 /* TX complete on queue 3 */
332 #define VGE_IMR_TXDMA_STALL 0x02000000 /* TX DMA STALL */
338 /* TX descriptor queue control/status register */
340 #define VGE_TXQCSR_RUN0 0x0001 /* Enable TX queue 0 */
344 #define VGE_TXQCSR_RUN1 0x0010 /* Enable TX queue 1 */
348 #define VGE_TXQCSR_RUN2 0x0100 /* Enable TX queue 2 */
352 #define VGE_TXQCSR_RUN3 0x1000 /* Enable TX queue 3 */
364 /* RX/TX queue empty interrupt delay timer register */
391 * holdoff timer, the TX interrupt supression count or the
431 #define VGE_PHYSTS_TXFLOWCAP 0x01 /* resolved TX flow control cap */
485 #define VGE_DMACFG0_BURSTLEN 0x07 /* RX/TX DMA burst (in dwords) */
512 #define VGE_VTAG_OPT0 0x00 /* TX: no tag insertion
515 #define VGE_VTAG_OPT1 0x02 /* TX: no tag insertion
519 #define VGE_VTAG_OPT2 0x04 /* TX: perform tag insertion,
522 #define VGE_VTAG_OPT3 0x06 /* TX: perform tag insertion,
531 /* TX MAC config register */
537 #define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */
665 * Each TX DMA descriptor has a control and status word, and 7
679 * Normally, the chip requires the driver to issue a TX poll command
680 * for every packet that gets put in the TX DMA queue. Sometimes though,
694 #define VGE_TDSTS_COLLCNT 0x0000000F /* TX collision count */
697 #define VGE_TDSTS_OWT 0x00000040 /* jumbo frame tx abort */
698 #define VGE_TDSTS_EXCESSCOLL 0x00000080 /* TX aborted, excess colls */
701 #define VGE_TDSTS_SHUTDOWN 0x00000400 /* shutdown during TX */
702 #define VGE_TDSTS_LINKFAIL 0x00001000 /* link fail during TX */
738 * Like the TX descriptor, the high bit in the buflen field in the