Lines Matching +full:poll +full:- +full:retry +full:- +full:count

1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
18  * 4. Neither the name of the author nor the names of any co-contributors
37  * Definitions for the built-in copper PHY can be found in vgphy.h.
41  * using 32-bit I/O cycles, but some of them are less than 32 bits
105 #define VGE_RXDESC_RESIDUECNT	0x5E	/* RX descriptor residue count */
119 #define VGE_SSTIMER		0x74	/* single-shot timer */
196 #define VGE_TXCTL_COLLCTL		0x0C /* collision retry control */
205 #define VGE_TXCOLLS_INFINITE		0x0C /* retry forever */
233 #define VGE_CR3_INT_SWPEND		0x01 /* disable multi-level int bits */
279 #define VGE_ISR_RXCNTOFLOW	0x00000400 /* RX packet count overflow */
317 #define VGE_IMR_RXCNTOFLOW	0x00000400 /* RX packet count overflow */
342 #define VGE_TXQCSR_WAK0		0x0004	/* Wake up (poll) queue 0 */
346 #define VGE_TXQCSR_WAK1		0x0040	/* Wake up (poll) queue 1 */
350 #define VGE_TXQCSR_WAK2		0x0400	/* Wake up (poll) queue 2 */
354 #define VGE_TXQCSR_WAK3		0x4000	/* Wake up (poll) queue 3 */
361 #define VGE_RXQCSR_WAK		0x0004	/* Wake up (poll) queue */
386  * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the
389  * - The behavior of the interrupt holdoff timer register at offset
391  *   holdoff timer, the TX interrupt supression count or the
392  *   RX interrupt supression count)
393  * - The behavior the WOL pattern programming registers at offset
427 #define VGE_MIISTS_IIDL		0x80	/* not at sofrware/timer poll cycle */
456 #define VGE_CHIPCFG0_PACPI	0x01	/* pre-ACPI wakeup function */
537 #define VGE_TXCFG_NONBLK	0x02	/* priority TX/non-blocking mode */
538 #define VGE_TXCFG_NONBLK_THR	0x0C	/* non-blocking threshold */
590 #define	VGE_MIB_CNT		(VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1)
679  * Normally, the chip requires the driver to issue a TX poll command
694 #define VGE_TDSTS_COLLCNT	0x0000000F	/* TX collision count */