Lines Matching +full:0 +full:x0402
24 #define RAL_FRAME_SIZE 0x780 /* NOTE: using 0x980 does not work */
27 #define RAL_IFACE_INDEX 0
29 #define RAL_VENDOR_REQUEST 0x01
30 #define RAL_WRITE_MAC 0x02
31 #define RAL_READ_MAC 0x03
32 #define RAL_WRITE_MULTI_MAC 0x06
33 #define RAL_READ_MULTI_MAC 0x07
34 #define RAL_READ_EEPROM 0x09
39 #define RAL_MAC_CSR0 0x0400 /* ASIC Version */
40 #define RAL_MAC_CSR1 0x0402 /* System control */
41 #define RAL_MAC_CSR2 0x0404 /* MAC addr0 */
42 #define RAL_MAC_CSR3 0x0406 /* MAC addr1 */
43 #define RAL_MAC_CSR4 0x0408 /* MAC addr2 */
44 #define RAL_MAC_CSR5 0x040a /* BSSID0 */
45 #define RAL_MAC_CSR6 0x040c /* BSSID1 */
46 #define RAL_MAC_CSR7 0x040e /* BSSID2 */
47 #define RAL_MAC_CSR8 0x0410 /* Max frame length */
48 #define RAL_MAC_CSR9 0x0412 /* Timer control */
49 #define RAL_MAC_CSR10 0x0414 /* Slot time */
50 #define RAL_MAC_CSR11 0x0416 /* IFS */
51 #define RAL_MAC_CSR12 0x0418 /* EIFS */
52 #define RAL_MAC_CSR13 0x041a /* Power mode0 */
53 #define RAL_MAC_CSR14 0x041c /* Power mode1 */
54 #define RAL_MAC_CSR15 0x041e /* Power saving transition0 */
55 #define RAL_MAC_CSR16 0x0420 /* Power saving transition1 */
56 #define RAL_MAC_CSR17 0x0422 /* Power state control */
57 #define RAL_MAC_CSR18 0x0424 /* Auto wake-up control */
58 #define RAL_MAC_CSR19 0x0426 /* GPIO control */
59 #define RAL_MAC_CSR20 0x0428 /* LED control0 */
60 #define RAL_MAC_CSR22 0x042c /* XXX not documented */
65 #define RAL_TXRX_CSR0 0x0440 /* Security control */
66 #define RAL_TXRX_CSR2 0x0444 /* Rx control */
67 #define RAL_TXRX_CSR5 0x044a /* CCK Tx BBP ID0 */
68 #define RAL_TXRX_CSR6 0x044c /* CCK Tx BBP ID1 */
69 #define RAL_TXRX_CSR7 0x044e /* OFDM Tx BBP ID0 */
70 #define RAL_TXRX_CSR8 0x0450 /* OFDM Tx BBP ID1 */
71 #define RAL_TXRX_CSR10 0x0454 /* Auto responder control */
72 #define RAL_TXRX_CSR11 0x0456 /* Auto responder basic rate */
73 #define RAL_TXRX_CSR18 0x0464 /* Beacon interval */
74 #define RAL_TXRX_CSR19 0x0466 /* Beacon/sync control */
75 #define RAL_TXRX_CSR20 0x0468 /* Beacon alignment */
76 #define RAL_TXRX_CSR21 0x046a /* XXX not documented */
81 #define RAL_SEC_CSR0 0x0480 /* Shared key 0, word 0 */
86 #define RAL_PHY_CSR2 0x04c4 /* Tx MAC configuration */
87 #define RAL_PHY_CSR4 0x04c8 /* Interface configuration */
88 #define RAL_PHY_CSR5 0x04ca /* BBP Pre-Tx CCK */
89 #define RAL_PHY_CSR6 0x04cc /* BBP Pre-Tx OFDM */
90 #define RAL_PHY_CSR7 0x04ce /* BBP serial control */
91 #define RAL_PHY_CSR8 0x04d0 /* BBP serial status */
92 #define RAL_PHY_CSR9 0x04d2 /* RF serial control0 */
93 #define RAL_PHY_CSR10 0x04d4 /* RF serial control1 */
98 #define RAL_STA_CSR0 0x04e0 /* FCS error */
100 #define RAL_DISABLE_RX (1 << 0)
112 #define RAL_RESET_ASIC (1 << 0)
116 #define RAL_ENABLE_TSF (1 << 0)
117 #define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1)
125 #define RAL_BBP_BUSY (1 << 0)
127 #define RAL_RF1_AUTOTUNE 0x08000
128 #define RAL_RF3_AUTOTUNE 0x00040
130 #define RAL_RF_2522 0x00
131 #define RAL_RF_2523 0x01
132 #define RAL_RF_2524 0x02
133 #define RAL_RF_2525 0x03
134 #define RAL_RF_2525E 0x04
135 #define RAL_RF_2526 0x05
137 #define RAL_RF_5222 0x10
139 #define RAL_BBP_VERSION 0
143 #define RAL_BBP_ANTA 0x00
144 #define RAL_BBP_DIVERSITY 0x01
145 #define RAL_BBP_ANTB 0x02
146 #define RAL_BBP_ANTMASK 0x03
147 #define RAL_BBP_FLIPIQ 0x04
149 #define RAL_JAPAN_FILTER 0x08
160 #define RAL_TX_IFS_MASK 0x00006000
161 #define RAL_TX_IFS_BACKOFF (0 << 13)
167 #define RAL_LOGCWMAX(x) (((x) & 0xf) << 12)
168 #define RAL_LOGCWMIN(x) (((x) & 0xf) << 8)
169 #define RAL_AIFSN(x) (((x) & 0x3) << 6)
170 #define RAL_IVOFFSET(x) (((x) & 0x3f))
175 #define RAL_PLCP_LENGEXT 0x80
201 #define RAL_RF1 0
206 #define RAL_EEPROM_ADDRESS 0x0004
207 #define RAL_EEPROM_TXPOWER 0x003c
208 #define RAL_EEPROM_CONFIG0 0x0016
209 #define RAL_EEPROM_BBP_BASE 0x001c