156 static void		ural_write(struct ural_softc *, uint16_t, uint16_t);
688 			ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_newstate()
691 			ural_write(sc, RAL_MAC_CSR20, 0);  in ural_newstate()
726 		ural_write(sc, RAL_MAC_CSR20, 1);  in ural_newstate()
1437 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)  in ural_write()  function
1492 	ural_write(sc, RAL_PHY_CSR7, tmp);  in ural_bbp_write()
1502 	ural_write(sc, RAL_PHY_CSR7, val);  in ural_bbp_read()
1536 	ural_write(sc, RAL_PHY_CSR9,  tmp & 0xffff);  in ural_rf_write()
1537 	ural_write(sc, RAL_PHY_CSR10, tmp >> 16);  in ural_rf_write()
1551 	ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_scan_start()
1736 	ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_enable_tsf_sync()
1739 	ural_write(sc, RAL_TXRX_CSR18, tmp);  in ural_enable_tsf_sync()
1744 	ural_write(sc, RAL_TXRX_CSR20, tmp);  in ural_enable_tsf_sync()
1752 	ural_write(sc, RAL_TXRX_CSR19, tmp);  in ural_enable_tsf_sync()
1761 	ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_enable_tsf()
1762 	ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2));  in ural_enable_tsf()
1786 	ural_write(sc, RAL_MAC_CSR10, slottime);  in ural_update_slot()
1787 	ural_write(sc, RAL_MAC_CSR11, sifs);  in ural_update_slot()
1788 	ural_write(sc, RAL_MAC_CSR12, eifs);  in ural_update_slot()
1803 	ural_write(sc, RAL_TXRX_CSR10, tmp);  in ural_set_txpreamble()
1813 		ural_write(sc, RAL_TXRX_CSR11, 0x150);  in ural_set_basicrates()
1816 		ural_write(sc, RAL_TXRX_CSR11, 0x15f);  in ural_set_basicrates()
1819 		ural_write(sc, RAL_TXRX_CSR11, 0x3);  in ural_set_basicrates()
1829 	ural_write(sc, RAL_MAC_CSR5, tmp);  in ural_set_bssid()
1832 	ural_write(sc, RAL_MAC_CSR6, tmp);  in ural_set_bssid()
1835 	ural_write(sc, RAL_MAC_CSR7, tmp);  in ural_set_bssid()
1846 	ural_write(sc, RAL_MAC_CSR2, tmp);  in ural_set_macaddr()
1849 	ural_write(sc, RAL_MAC_CSR3, tmp);  in ural_set_macaddr()
1852 	ural_write(sc, RAL_MAC_CSR4, tmp);  in ural_set_macaddr()
1868 	ural_write(sc, RAL_TXRX_CSR2, tmp);  in ural_setpromisc()
1981 	ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7));  in ural_set_txantenna()
1984 	ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7));  in ural_set_txantenna()
2018 	ural_write(sc, 0x308, 0x00f0);	/* XXX magic */  in ural_init()
2024 		ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);  in ural_init()
2042 	ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY);  in ural_init()
2045 	ural_write(sc, RAL_TXRX_CSR11, 0x15f);  in ural_init()
2074 	ural_write(sc, RAL_TXRX_CSR2, tmp);  in ural_init()
2103 	ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX);  in ural_stop()
2105 	ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP);  in ural_stop()
2108 	ural_write(sc, RAL_MAC_CSR1, 0);  in ural_stop()