Lines Matching +full:0 +full:x2e00
19 #define MTW_ASIC_VER 0x0000
20 #define MTW_CMB_CTRL 0x0020
21 #define MTW_EFUSE_CTRL 0x0024
22 #define MTW_EFUSE_DATA0 0x0028
23 #define MTW_EFUSE_DATA1 0x002c
24 #define MTW_EFUSE_DATA2 0x0030
25 #define MTW_EFUSE_DATA3 0x0034
26 #define MTW_OSC_CTRL 0x0038
27 #define MTW_COEX_CFG0 0x0040
28 #define MTW_PLL_CTRL 0x0050
29 #define MTW_LDO_CFG0 0x006c
30 #define MTW_LDO_CFG1 0x0070
31 #define MTW_WLAN_CTRL 0x0080
34 #define MTW_INT_STATUS 0x0200
35 #define RT2860_INT_MASK 0x0204
36 #define MTW_WPDMA_GLO_CFG 0x0208
37 #define RT2860_WPDMA_RST_IDX 0x020c
38 #define RT2860_DELAY_INT_CFG 0x0210
39 #define MTW_WMM_AIFSN_CFG 0x0214
40 #define MTW_WMM_CWMIN_CFG 0x0218
41 #define MTW_WMM_CWMAX_CFG 0x021c
42 #define MTW_WMM_TXOP0_CFG 0x0220
43 #define MTW_WMM_TXOP1_CFG 0x0224
44 #define RT2860_GPIO_CTRL 0x0228
45 #define RT2860_MCU_CMD_REG 0x022c
46 #define MTW_MCU_DMA_ADDR 0x0230
47 #define MTW_MCU_DMA_LEN 0x0234
48 #define MTW_USB_DMA_CFG 0x0238
49 #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16)
50 #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16)
51 #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16)
52 #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16)
53 #define MTW_TSO_CTRL 0x0250
54 #define MTW_HDR_TRANS_CTRL 0x0260
55 #define RT2860_RX_BASE_PTR 0x0290
56 #define RT2860_RX_MAX_CNT 0x0294
57 #define RT2860_RX_CALC_IDX 0x0298
58 #define RT2860_FS_DRX_IDX 0x029c
59 #define MTW_US_CYC_CNT 0x02a4
61 #define MTW_TX_RING_BASE 0x0300
62 #define MTW_RX_RING_BASE 0x03c0
65 #define MTW_SYS_CTRL 0x0400
66 #define MTW_PBF_CFG 0x0404
67 #define MTW_TX_MAX_PCNT 0x0408
68 #define MTW_RX_MAX_PCNT 0x040c
69 #define MTW_PBF_CTRL 0x0410
70 #define RT2860_BUF_CTRL 0x0410
71 #define RT2860_MCU_INT_STA 0x0414
72 #define RT2860_MCU_INT_ENA 0x0418
73 #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4)
74 #define MTW_BCN_OFFSET0 0x041c
75 #define MTW_BCN_OFFSET1 0x0420
76 #define MTW_BCN_OFFSET2 0x0424
77 #define MTW_BCN_OFFSET3 0x0428
78 #define RT2860_RX0Q_IO 0x0424
79 #define MTW_RXQ_STA 0x0430
80 #define MTW_TXQ_STA 0x0434
81 #define MTW_TXRXQ_PCNT 0x0438
84 #define MTW_RF_CSR 0x0500
85 #define MTW_RF_BYPASS0 0x0504
86 #define MTW_RF_BYPASS1 0x0508
87 #define MTW_RF_SETTING0 0x050C
88 #define MTW_RF_MISC 0x0518
89 #define MTW_RF_DATA_WR 0x0524
90 #define MTW_RF_CTRL 0x0528
91 #define MTW_RF_DATA_RD 0x052c
94 #define MTW_MCU_RESET_CTL 0x070c
95 #define MTW_MCU_INT_LEVEL 0x0718
96 #define MTW_MCU_COM_REG0 0x0730
97 #define MTW_MCU_COM_REG1 0x0734
98 #define MTW_MCU_COM_REG2 0x0738
99 #define MTW_MCU_COM_REG3 0x073c
100 #define MTW_FCE_PSE_CTRL 0x0800
101 #define MTW_FCE_PARAMETERS 0x0804
102 #define MTW_FCE_CSO 0x0808
103 #define MTW_FCE_L2_STUFF 0x080c
104 #define MTW_FCE_WLAN_FLOW_CTRL 0x0824
105 #define MTW_TX_CPU_FCE_BASE 0x09a0
106 #define MTW_TX_CPU_FCE_MAX_COUNT 0x09a4
107 #define MTW_MCU_FW_IDX 0x09a8
108 #define MTW_FCE_PDMA 0x09c4
109 #define MTW_FCE_SKIP_FS 0x0a6c
112 #define MTW_MAC_VER_ID 0x1000
113 #define MTW_MAC_SYS_CTRL 0x1004
114 #define MTW_MAC_ADDR_DW0 0x1008
115 #define MTW_MAC_ADDR_DW1 0x100c
116 #define MTW_MAC_BSSID_DW0 0x1010
117 #define MTW_MAC_BSSID_DW1 0x1014
118 #define MTW_MAX_LEN_CFG 0x1018
119 #define MTW_BBP_CSR 0x101c
120 #define MTW_LED_CFG 0x102c
121 #define MTW_AMPDU_MAX_LEN_20M1S 0x1030
122 #define MTW_AMPDU_MAX_LEN_20M2S 0x1034
123 #define MTW_AMPDU_MAX_LEN_40M1S 0x1038
124 #define MTW_AMPDU_MAX_LEN_40M2S 0x103c
125 #define MTW_AMPDU_MAX_LEN 0x1040
128 #define MTW_XIFS_TIME_CFG 0x1100
129 #define MTW_BKOFF_SLOT_CFG 0x1104
130 #define RT2860_NAV_TIME_CFG 0x1108
131 #define RT2860_CH_TIME_CFG 0x110c
132 #define RT2860_PBF_LIFE_TIMER 0x1110
133 #define MTW_BCN_TIME_CFG 0x1114
134 #define MTW_TBTT_SYNC_CFG 0x1118
135 #define MTW_TSF_TIMER_DW0 0x111c
136 #define MTW_TSF_TIMER_DW1 0x1120
137 #define RT2860_TBTT_TIMER 0x1124
138 #define MTW_INT_TIMER_CFG 0x1128
139 #define RT2860_INT_TIMER_EN 0x112c
140 #define RT2860_CH_IDLE_TIME 0x1130
143 #define MTW_MAC_STATUS_REG 0x1200
144 #define MTW_PWR_PIN_CFG 0x1204
145 #define MTW_AUTO_WAKEUP_CFG 0x1208
146 #define MTW_AUX_CLK_CFG 0x120c
147 #define MTW_BBP_PA_MODE_CFG0 0x1214
148 #define MTW_BBP_PA_MODE_CFG1 0x1218
149 #define MTW_RF_PA_MODE_CFG0 0x121c
150 #define MTW_RF_PA_MODE_CFG1 0x1220
151 #define MTW_RF_PA_MODE_ADJ0 0x1228
152 #define MTW_RF_PA_MODE_ADJ1 0x122c
153 #define MTW_DACCLK_EN_DLY_CFG 0x1264 /* MT7612 */
156 #define MTW_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4)
157 #define MTW_EDCA_TID_AC_MAP 0x1310
158 #define MTW_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4)
159 #define MTW_TX_PIN_CFG 0x1328
160 #define MTW_TX_BAND_CFG 0x132c
161 #define MTW_TX_SW_CFG0 0x1330
162 #define MTW_TX_SW_CFG1 0x1334
163 #define MTW_TX_SW_CFG2 0x1338
164 #define RT2860_TXOP_THRES_CFG 0x133c
165 #define MTW_TXOP_CTRL_CFG 0x1340
166 #define MTW_TX_RTS_CFG 0x1344
167 #define MTW_TX_TIMEOUT_CFG 0x1348
168 #define MTW_TX_RETRY_CFG 0x134c
169 #define MTW_TX_LINK_CFG 0x1350
170 #define MTW_HT_FBK_CFG0 0x1354
171 #define MTW_HT_FBK_CFG1 0x1358
172 #define MTW_LG_FBK_CFG0 0x135c
173 #define MTW_LG_FBK_CFG1 0x1360
174 #define MTW_CCK_PROT_CFG 0x1364
175 #define MTW_OFDM_PROT_CFG 0x1368
176 #define MTW_MM20_PROT_CFG 0x136c
177 #define MTW_MM40_PROT_CFG 0x1370
178 #define MTW_GF20_PROT_CFG 0x1374
179 #define MTW_GF40_PROT_CFG 0x1378
180 #define RT2860_EXP_CTS_TIME 0x137c
181 #define MTW_EXP_ACK_TIME 0x1380
182 #define MTW_TX_PWR_CFG5 0x1384
183 #define MTW_TX_PWR_CFG6 0x1388
184 #define MTW_TX_PWR_EXT_CFG(ridx) (0x1390 + (ridx) * 4)
185 #define MTW_TX0_RF_GAIN_CORR 0x13a0
186 #define MTW_TX1_RF_GAIN_CORR 0x13a4
187 #define MTW_TX0_RF_GAIN_ATTEN 0x13a8
188 #define MTW_TX_ALC_CFG3 0x13ac
189 #define MTW_TX_ALC_CFG0 0x13b0
190 #define MTW_TX_ALC_CFG1 0x13b4
191 #define MTW_TX_ALC_CFG4 0x13c0
192 #define MTW_TX_ALC_VGA3 0x13c8
193 #define MTW_TX_PWR_CFG7 0x13d4
194 #define MTW_TX_PWR_CFG8 0x13d8
195 #define MTW_TX_PWR_CFG9 0x13dc
196 #define MTW_VHT20_PROT_CFG 0x13e0
197 #define MTW_VHT40_PROT_CFG 0x13e4
198 #define MTW_VHT80_PROT_CFG 0x13e8
199 #define MTW_TX_PIFS_CFG 0x13ec /* MT761X */
202 #define MTW_RX_FILTR_CFG 0x1400
203 #define MTW_AUTO_RSP_CFG 0x1404
204 #define MTW_LEGACY_BASIC_RATE 0x1408
205 #define MTW_HT_BASIC_RATE 0x140c
206 #define MTW_HT_CTRL_CFG 0x1410
207 #define RT2860_SIFS_COST_CFG 0x1414
208 #define RT2860_RX_PARSER_CFG 0x1418
211 #define RT2860_TX_SEC_CNT0 0x1500
212 #define RT2860_RX_SEC_CNT0 0x1504
213 #define RT2860_CCMP_FC_MUTE 0x1508
214 #define MTW_PN_PAD_MODE 0x150c /* MT761X */
217 #define MTW_TXOP_HLDR_ADDR0 0x1600
218 #define MTW_TXOP_HLDR_ADDR1 0x1604
219 #define MTW_TXOP_HLDR_ET 0x1608
220 #define RT2860_QOS_CFPOLL_RA_DW0 0x160c
221 #define RT2860_QOS_CFPOLL_A1_DW1 0x1610
222 #define RT2860_QOS_CFPOLL_QC 0x1614
223 #define MTW_PROT_AUTO_TX_CFG 0x1648
226 #define MTW_RX_STA_CNT0 0x1700
227 #define MTW_RX_STA_CNT1 0x1704
228 #define MTW_RX_STA_CNT2 0x1708
229 #define MTW_TX_STA_CNT0 0x170c
230 #define MTW_TX_STA_CNT1 0x1710
231 #define MTW_TX_STA_CNT2 0x1714
232 #define MTW_TX_STAT_FIFO 0x1718
235 #define MTW_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8)
238 #define MTW_BBP_CORE(x) (0x2000 + (x) * 4)
239 #define MTW_BBP_IBI(x) (0x2100 + (x) * 4)
240 #define MTW_BBP_AGC(x) (0x2300 + (x) * 4)
241 #define MTW_BBP_TXC(x) (0x2400 + (x) * 4)
242 #define MTW_BBP_RXC(x) (0x2500 + (x) * 4)
243 #define MTW_BBP_TXQ(x) (0x2600 + (x) * 4)
244 #define MTW_BBP_TXBE(x) (0x2700 + (x) * 4)
245 #define MTW_BBP_RXFE(x) (0x2800 + (x) * 4)
246 #define MTW_BBP_RXO(x) (0x2900 + (x) * 4)
247 #define MTW_BBP_DFS(x) (0x2a00 + (x) * 4)
248 #define MTW_BBP_TR(x) (0x2b00 + (x) * 4)
249 #define MTW_BBP_CAL(x) (0x2c00 + (x) * 4)
250 #define MTW_BBP_DSC(x) (0x2e00 + (x) * 4)
251 #define MTW_BBP_PFMU(x) (0x2f00 + (x) * 4)
253 #define MTW_SKEY_MODE_16_23 0x7008
254 #define MTW_SKEY_MODE_24_31 0x700c
255 #define MTW_H2M_MAILBOX 0x7010
258 #define MTW_PKEY(wcid) (0x8000 + (wcid) * 32)
261 #define MTW_USB_U3DMA_CFG 0x9018
264 #define MTW_IVEIV(wcid) (0xa000 + (wcid) * 8)
267 #define MTW_WCID_ATTR(wcid) (0xa800 + (wcid) * 4)
272 #define MTW_SKEY_0(vap, kidx) (0xac00 + (4 * (vap) + (kidx)) * 32)
273 #define MTW_SKEY_1(vap, kidx) (0xb400 + (4 * ((vap) & 7) + (kidx)) * 32)
276 #define MTW_SKEY_MODE_0_7 0xb000
277 #define MTW_SKEY_MODE_8_15 0xb004
280 #define MTW_SKEY_MODE_BASE 0xb000
283 #define MTW_BCN_BASE 0xc000
285 /* possible flags for register CMB_CTRL 0x0020 */
289 /* possible flags for register EFUSE_CTRL 0x0024 */
292 #define MTW_EFSROM_AIN_MASK 0x03ff0000
294 #define MTW_EFSROM_MODE_MASK 0x000000c0
295 #define MTW_EFUSE_AOUT_MASK 0x0000003f
297 /* possible flags for register OSC_CTRL 0x0038 */
302 #define MTW_OSC_CAL_CNT (0xfff << 16)
303 #define MTW_OSC_REF_CYCLE 0x1fff
305 /* possible flags for register WLAN_CTRL 0x0080 */
306 #define MTW_GPIO_OUT_OE_ALL (0xff << 24)
307 #define MTW_GPIO_OUT_ALL (0xff << 16)
308 #define MTW_GPIO_IN_ALL (0xff << 8)
317 #define MTW_WLAN_EN (1U << 0)
319 /* possible flags for registers INT_STATUS/INT_MASK 0x0200 */
337 #define RT2860_RX_DLY_INT (1 << 0)
339 /* possible flags for register WPDMA_GLO_CFG 0x0208 */
344 #define MTW_WPDMA_BT_SIZE16 0
351 #define MTW_TX_DMA_EN (1 << 0)
359 #define RT2860_RXMAX_PTIME_SHIFT 0
363 #define RT2860_GPIO_O_SHIFT 0
365 /* possible flags for register MCU_DMA_ADDR 0x0230 */
366 #define MTW_MCU_READY (1U << 0)
368 /* possible flags for register USB_DMA_CFG 0x0238 */
381 #define MTW_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */
383 /* possible flags for register US_CYC_CNT 0x02a4 */
387 #define RT2860_US_CYC_CNT_SHIFT 0
389 /* possible flags for register PBF_CFG 0x0404 */
395 #define MTW_PBF_CFG_TX0Q_EN (1 << 0)
397 /* possible flags for register BUF_CTRL 0x0410 */
403 #define RT2860_READ_RX0Q (1 << 0)
425 #define RT2860_MRX0_INT (1 << 0)
427 /* possible flags for register TXRXQ_PCNT 0x0438 */
428 #define MTW_RX0Q_PCNT_MASK 0xff000000
429 #define MTW_TX2Q_PCNT_MASK 0x00ff0000
430 #define MTW_TX1Q_PCNT_MASK 0x0000ff00
431 #define MTW_TX0Q_PCNT_MASK 0x000000ff
433 /* possible flags for register RF_CSR_CFG 0x0500 */
439 /* possible flags for register FCE_L2_STUFF 0x080c */
445 /* possible flags for register MAC_SYS_CTRL 0x1004 */
453 #define MTW_MAC_SRST (1 << 0)
455 /* possible flags for register MAC_BSSID_DW1 0x100c */
459 /* possible flags for register MAX_LEN_CFG 0x1018 */
462 #define RT2860_MAX_PSDU_LEN8K 0
466 #define RT2860_MAX_MPDU_LEN_SHIFT 0
468 /* possible flags for registers BBP_CSR_CFG 0x101c */
472 #define MTW_BBP_DATA_SHIFT 0
475 #define MTW_LED_MODE_ON 0
480 /* possible flags for register XIFS_TIME_CFG 0x1100 */
485 #define MTW_CCK_SIFS_TIME_SHIFT 0
487 /* possible flags for register BKOFF_SLOT_CFG 0x1104 */
489 #define MTW_SLOT_TIME 0
495 #define RT2860_NAV_TIMER_SHIFT 0
502 #define RT2860_CH_STA_TIMER_EN (1 << 0)
504 /* possible values for register BCN_TIME_CFG 0x1114 */
509 #define MTW_TSF_SYNC_MODE_DIS 0
514 #define MTW_BCN_INTVAL_SHIFT 0
516 /* possible flags for register TBTT_SYNC_CFG 0x1118 */
520 #define RT2860_TBTT_ADJUST_SHIFT 0
522 /* possible flags for register INT_TIMER_CFG 0x1128 */
524 #define RT2860_PRE_TBTT_TIMER_SHIFT 0
528 #define RT2860_PRE_TBTT_INT_EN (1 << 0)
530 /* possible flags for register MAC_STATUS_REG 0x1200 */
532 #define MTW_TX_STATUS_BUSY (1 << 0)
534 /* possible flags for register PWR_PIN_CFG 0x1204 */
538 #define RT2860_IO_RF_PE (1 << 0)
540 /* possible flags for register AUTO_WAKEUP_CFG 0x1208 */
543 #define MTW_WAKEUP_LEAD_TIME_SHIFT 0
545 /* possible flags for register TX_PIN_CFG 0x1328 */
567 #define RT2860_PA_PE_A0_EN (1U << 0)
569 /* possible flags for register TX_BAND_CFG 0x132c */
572 #define MTW_TX_BAND_UPPER_40M (1 << 0)
574 /* possible flags for register TX_SW_CFG0 0x1330 */
578 #define RT2860_DLY_TXPE_EN_SHIFT 0
580 /* possible flags for register TX_SW_CFG1 0x1334 */
583 #define RT2860_DLY_PAPE_DIS SHIFT 0
585 /* possible flags for register TX_SW_CFG2 0x1338 */
589 #define RT2860_DLY_DAC_DIS_SHIFT 0
591 /* possible flags for register TXOP_THRES_CFG 0x133c */
595 #define RT2860_RDG_OUT_THRES 0
597 /* possible flags for register TXOP_CTRL_CFG 0x1340 */
607 #define MTW_TXOP_TRUN_EN_TIMEOUT (1 << 0)
609 /* possible flags for register TX_RTS_CFG 0x1344 */
612 #define MTW_RTS_RTY_LIMIT_SHIFT 0
614 /* possible flags for register TX_TIMEOUT_CFG 0x1348 */
619 /* possible flags for register TX_RETRY_CFG 0x134c */
625 #define MTW_SHORT_RTY_LIMIT_SHIFT 0
627 /* possible flags for register TX_LINK_CFG 0x1350 */
635 #define MTW_REMOTE_MFB_LT_SHIFT 0
645 #define RT2860_TXOP_ALLOW_ALL (0x3f << 20)
653 #define RT2860_EXP_CCK_TIME_SHIFT 0
655 /* possible flags for register RX_FILTR_CFG 0x1400 */
672 #define MTW_DROP_CRC_ERR (1 << 0)
674 /* possible flags for register AUTO_RSP_CFG 0x1404 */
681 #define MTW_AUTO_RSP_EN (1 << 0)
685 #define RT2860_CCK_SIFS_COST_SHIFT 0
687 /* possible flags for register TXOP_HLDR_ET 0x1608 */
693 #define MTW_PER_RX_RST_EN (1 << 0)
695 /* possible flags for register TX_STAT_FIFO 0x1718 */
702 #define MTW_TXQ_VLD (1 << 0)
704 /* possible flags for register TX_STAT_FIFO_EXT 0x1798 */
706 #define MTW_TXQ_RETRY_SHIFT 0
708 /* possible flags for register WCID_ATTR 0xa800 */
709 #define MTW_MODE_NOSEC 0
717 #define MTW_RX_PKEY_EN (1 << 0)
720 #define MT7601_R47_MASK 0x07
721 #define MT7601_R47_TSSI (0 << 0)
722 #define MT7601_R47_PKT (1 << 0)
726 #define MTW_RXQ_WLAN 0
740 uint32_t sdp0; /* Segment Data Pointer 0 */
745 uint16_t sdl0; /* Segment Data Length 0 */
753 #define RT2860_TX_QSEL_MGMT (0 << 1)
756 #define RT2860_TX_WIV (1 << 0)
764 #define MTW_TXD_DATA (0 << 14)
766 #define MTW_TXD_WLAN (0 << 11)
769 #define MTW_TXD_QSEL_MGMT (0 << 9)
777 uint8_t fw[0x2c44];
787 #define MTW_TX_FRAG (1 << 0)
790 #define MTW_TX_TXOP_HT 0
796 #define MT7650_PHY_MODE 0xe000
797 #define MT7601_PHY_MODE 0xc000
802 #define MTW_PHY_BW20 (0 << 7)
807 #define MTW_PHY_MCS 0x3f
813 #define MTW_TX_ACK (1 << 0)
850 #define MTW_RX_BA (1 << 0)
857 #define MTW_RXD_LEN 0x3fff
902 #define MT7601_RF_7601 0x7601 /* 1T1R */
903 #define MT7610_RF_7610 0x7610 /* 1T1R */
904 #define MT7612_RF_7612 0x7612 /* 2T2R */
909 #define MTW_RESET 0x1
910 #define MTW_WRITE_2 0x2
911 #define MTW_WRITE_REGION_1 0x6
912 #define MTW_READ_REGION_1 0x7
913 #define MTW_EEPROM_READ 0x9
914 #define MTW_WRITE_CFG 0x46
915 #define MTW_READ_CFG 0x47
918 #define MTW_EEPROM_CHIPID 0x00
919 #define MTW_EEPROM_VERSION 0x01
920 #define MTW_EEPROM_MAC01 0x02
921 #define MTW_EEPROM_MAC23 0x03
922 #define MTW_EEPROM_MAC45 0x04
923 #define MTW_EEPROM_ANTENNA 0x1a
924 #define MTW_EEPROM_CONFIG 0x1b
925 #define MTW_EEPROM_COUNTRY 0x1c
926 #define MTW_EEPROM_FREQ_OFFSET 0x1d
927 #define MTW_EEPROM_LED1 0x1e
928 #define MTW_EEPROM_LED2 0x1f
929 #define MTW_EEPROM_LED3 0x20
930 #define MTW_EEPROM_LNA 0x22
931 #define MTW_EEPROM_RSSI1_2GHZ 0x23
932 #define MTW_EEPROM_RSSI2_2GHZ 0x24
933 #define MTW_EEPROM_RSSI1_5GHZ 0x25
934 #define MTW_EEPROM_RSSI2_5GHZ 0x26
935 #define MTW_EEPROM_DELTAPWR 0x28
936 #define MTW_EEPROM_PWR2GHZ_BASE1 0x29
937 #define MTW_EEPROM_PWR2GHZ_BASE2 0x30
938 #define MTW_EEPROM_TSSI1_2GHZ 0x37
939 #define MTW_EEPROM_TSSI2_2GHZ 0x38
940 #define MTW_EEPROM_TSSI3_2GHZ 0x39
941 #define MTW_EEPROM_TSSI4_2GHZ 0x3a
942 #define MTW_EEPROM_TSSI5_2GHZ 0x3b
943 #define MTW_EEPROM_PWR5GHZ_BASE1 0x3c
944 #define MTW_NIC_CONF2 0x42
945 #define MTW_EEPROM_PWR5GHZ_BASE2 0x53
946 #define MTW_TXPWR_EXT_PA_5G 0x54
947 #define MTW_TXPWR_START_2G_0 0x56
948 #define MTW_TXPWR_START_2G_1 0x5c
949 #define MTW_TXPWR_START_5G_0 0x62
950 #define RT2860_EEPROM_TSSI1_5GHZ 0x6a
951 #define RT2860_EEPROM_TSSI2_5GHZ 0x6b
952 #define RT2860_EEPROM_TSSI3_5GHZ 0x6c
953 #define RT2860_EEPROM_TSSI4_5GHZ 0x6d
954 #define RT2860_EEPROM_TSSI5_5GHZ 0x6e
955 #define MTW_TX_TSSI_SLOPE 0x6e
956 #define MTW_EEPROM_RPWR 0x6f
959 #define CMD_LED_MODE 0x10
960 #define CMD_MODE_ON 0x0
969 { 2, 0, IEEE80211_T_DS, 0, 314, 314 },
973 { 12, 0, IEEE80211_T_OFDM, 4, 60, 60 },
981 { 0x80, 0, IEEE80211_T_HT, 4, 60, 60 },
982 { 0x81, 1, IEEE80211_T_HT, 4, 60, 60 },
983 { 0x82, 2, IEEE80211_T_HT, 4, 60, 60 },
984 { 0x83, 3, IEEE80211_T_HT, 4, 60, 60 },
985 { 0x84, 4, IEEE80211_T_HT, 4, 60, 60 },
986 { 0x85, 5, IEEE80211_T_HT, 4, 60, 60 },
987 { 0x86, 6, IEEE80211_T_HT, 4, 60, 60 },
988 { 0x87, 7, IEEE80211_T_HT, 4, 60, 60 },
989 { 0x88, 8, IEEE80211_T_HT, 4, 60, 60 },
990 { 0x89, 9, IEEE80211_T_HT, 4, 60, 60 },
991 { 0x8a, 10, IEEE80211_T_HT, 4, 60, 60 },
992 { 0x8b, 11, IEEE80211_T_HT, 4, 60, 60 },
993 { 0x8c, 12, IEEE80211_T_HT, 4, 60, 60 },
994 { 0x8d, 13, IEEE80211_T_HT, 4, 60, 60 },
995 { 0x8e, 14, IEEE80211_T_HT, 4, 60, 60 },
996 { 0x8f, 15, IEEE80211_T_HT, 4, 60, 60 },
999 { 0x90, 16, IEEE80211_T_HT, 4, 60, 60 },
1000 { 0x91, 17, IEEE80211_T_HT, 4, 60, 60 },
1001 { 0x92, 18, IEEE80211_T_HT, 4, 60, 60 },
1002 { 0x93, 19, IEEE80211_T_HT, 4, 60, 60 },
1003 { 0x94, 20, IEEE80211_T_HT, 4, 60, 60 },
1004 { 0x95, 21, IEEE80211_T_HT, 4, 60, 60 },
1005 { 0x96, 22, IEEE80211_T_HT, 4, 60, 60 },
1006 { 0x97, 23, IEEE80211_T_HT, 4, 60, 60 }
1009 #define MTW_RIDX_CCK1 0
1016 { 1, 0x99, 0x99, 0x09, 0x50 }, \
1017 { 2, 0x46, 0x44, 0x0a, 0x50 }, \
1018 { 3, 0xec, 0xee, 0x0a, 0x50 }, \
1019 { 4, 0x99, 0x99, 0x0b, 0x50 }, \
1020 { 5, 0x46, 0x44, 0x08, 0x51 }, \
1021 { 6, 0xec, 0xee, 0x08, 0x51 }, \
1022 { 7, 0x99, 0x99, 0x09, 0x51 }, \
1023 { 8, 0x46, 0x44, 0x0a, 0x51 }, \
1024 { 9, 0xec, 0xee, 0x0a, 0x51 }, \
1025 { 10, 0x99, 0x99, 0x0b, 0x51 }, \
1026 { 11, 0x46, 0x44, 0x08, 0x52 }, \
1027 { 12, 0xec, 0xee, 0x08, 0x52 }, \
1028 { 13, 0x99, 0x99, 0x09, 0x52 }, \
1029 { 14, 0x33, 0x33, 0x0b, 0x52 }
1035 { MTW_BCN_OFFSET0, 0x18100800 }, \
1036 { MTW_BCN_OFFSET1, 0x38302820 }, \
1037 { MTW_BCN_OFFSET2, 0x58504840 }, \
1038 { MTW_BCN_OFFSET3, 0x78706860 }, \
1039 { MTW_MAC_SYS_CTRL, 0x0000000c }, \
1040 { MTW_MAX_LEN_CFG, 0x000a3fff }, \
1041 { MTW_AMPDU_MAX_LEN_20M1S, 0x77777777 }, \
1042 { MTW_AMPDU_MAX_LEN_20M2S, 0x77777777 }, \
1043 { MTW_AMPDU_MAX_LEN_40M1S, 0x77777777 }, \
1044 { MTW_AMPDU_MAX_LEN_40M2S, 0x77777777 }, \
1045 { MTW_XIFS_TIME_CFG, 0x33a41010 }, \
1046 { MTW_BKOFF_SLOT_CFG, 0x00000209 }, \
1047 { MTW_TBTT_SYNC_CFG, 0x00422010 }, \
1048 { MTW_INT_TIMER_CFG, 0x00000000 }, \
1049 { MTW_PWR_PIN_CFG, 0x00000000 }, \
1050 { MTW_AUTO_WAKEUP_CFG, 0x00000014 }, \
1051 { MTW_EDCA_AC_CFG(0), 0x000a4360 }, \
1052 { MTW_EDCA_AC_CFG(1), 0x000a4700 }, \
1053 { MTW_EDCA_AC_CFG(2), 0x00043338 }, \
1054 { MTW_EDCA_AC_CFG(3), 0x0003222f }, \
1055 { MTW_TX_PIN_CFG, 0x33150f0f }, \
1056 { MTW_TX_BAND_CFG, 0x00000005 }, \
1057 { MTW_TX_SW_CFG0, 0x00000402 }, \
1058 { MTW_TX_SW_CFG1, 0x00000000 }, \
1059 { MTW_TX_SW_CFG2, 0x00000000 }, \
1060 { MTW_TXOP_CTRL_CFG, 0x0000583f }, \
1061 { MTW_TX_RTS_CFG, 0x01100020 }, \
1062 { MTW_TX_TIMEOUT_CFG, 0x000a2090 }, \
1063 { MTW_TX_RETRY_CFG, 0x47d01f0f }, \
1064 { MTW_TX_LINK_CFG, 0x007f1820 }, \
1065 { MTW_HT_FBK_CFG1, 0xedcba980 }, \
1066 { MTW_CCK_PROT_CFG, 0x07f40000 }, \
1067 { MTW_OFDM_PROT_CFG, 0x07f60000 }, \
1068 { MTW_MM20_PROT_CFG, 0x01750003 }, \
1069 { MTW_MM40_PROT_CFG, 0x03f50003 }, \
1070 { MTW_GF20_PROT_CFG, 0x01750003 }, \
1071 { MTW_GF40_PROT_CFG, 0x03f50003 }, \
1072 { MTW_EXP_ACK_TIME, 0x002400ca }, \
1073 { MTW_TX_PWR_CFG5, 0x00000000 }, \
1074 { MTW_TX_PWR_CFG6, 0x01010101 }, \
1075 { MTW_TX0_RF_GAIN_CORR, 0x003b0005 }, \
1076 { MTW_TX1_RF_GAIN_CORR, 0x00000000 }, \
1077 { MTW_TX0_RF_GAIN_ATTEN, 0x00006969 }, \
1078 { MTW_TX_ALC_CFG3, 0x6c6c6c6c }, \
1079 { MTW_TX_ALC_CFG0, 0x2f2f0005 }, \
1080 { MTW_TX_ALC_CFG4, 0x00000400 }, \
1081 { MTW_TX_ALC_VGA3, 0x00060006 }, \
1082 { MTW_RX_FILTR_CFG, 0x00015f97 }, \
1083 { MTW_AUTO_RSP_CFG, 0x00000003 }, \
1084 { MTW_LEGACY_BASIC_RATE, 0x0000015f }, \
1085 { MTW_HT_BASIC_RATE, 0x00008003 }, \
1086 { MTW_RX_MAX_PCNT, 0x0000009f }, \
1087 { MTW_WPDMA_GLO_CFG, 0x00000030 }, \
1088 { MTW_WMM_AIFSN_CFG, 0x00002273 }, \
1089 { MTW_WMM_CWMIN_CFG, 0x00002344 }, \
1090 { MTW_WMM_CWMAX_CFG, 0x000034aa }, \
1091 { MTW_TSO_CTRL, 0x00000000 }, \
1092 { MTW_SYS_CTRL, 0x00080c00 }, \
1093 { MTW_FCE_PSE_CTRL, 0x00000001 }, \
1094 { MTW_AUX_CLK_CFG, 0x00000000 }, \
1095 { MTW_BBP_PA_MODE_CFG0, 0x010055ff }, \
1096 { MTW_BBP_PA_MODE_CFG1, 0x00550055 }, \
1097 { MTW_RF_PA_MODE_CFG0, 0x010055ff }, \
1098 { MTW_RF_PA_MODE_CFG1, 0x00550055 }, \
1099 { 0x0a38, 0x00000000 }, \
1100 { MTW_BBP_CSR, 0x00000000 }, \
1101 { MTW_PBF_CFG, 0x7f723c1f }
1107 { 1, 0x04 }, \
1108 { 4, 0x40 }, \
1109 { 20, 0x06 }, \
1110 { 31, 0x08 }, \
1111 { 178, 0xff }, \
1112 { 66, 0x14 }, \
1113 { 68, 0x8b }, \
1114 { 69, 0x12 }, \
1115 { 70, 0x09 }, \
1116 { 73, 0x11 }, \
1117 { 75, 0x60 }, \
1118 { 76, 0x44 }, \
1119 { 84, 0x9a }, \
1120 { 86, 0x38 }, \
1121 { 91, 0x07 }, \
1122 { 92, 0x02 }, \
1123 { 99, 0x50 }, \
1124 { 101, 0x00 }, \
1125 { 103, 0xc0 }, \
1126 { 104, 0x92 }, \
1127 { 105, 0x3c }, \
1128 { 106, 0x03 }, \
1129 { 128, 0x12 }, \
1130 { 142, 0x04 }, \
1131 { 143, 0x37 }, \
1132 { 142, 0x03 }, \
1133 { 143, 0x99 }, \
1134 { 160, 0xeb }, \
1135 { 161, 0xc4 }, \
1136 { 162, 0x77 }, \
1137 { 163, 0xf9 }, \
1138 { 164, 0x88 }, \
1139 { 165, 0x80 }, \
1140 { 166, 0xff }, \
1141 { 167, 0xe4 }, \
1142 { 195, 0x00 }, \
1143 { 196, 0x00 }, \
1144 { 195, 0x01 }, \
1145 { 196, 0x04 }, \
1146 { 195, 0x02 }, \
1147 { 196, 0x20 }, \
1148 { 195, 0x03 }, \
1149 { 196, 0x0a }, \
1150 { 195, 0x06 }, \
1151 { 196, 0x16 }, \
1152 { 195, 0x07 }, \
1153 { 196, 0x05 }, \
1154 { 195, 0x08 }, \
1155 { 196, 0x37 }, \
1156 { 195, 0x0a }, \
1157 { 196, 0x15 }, \
1158 { 195, 0x0b }, \
1159 { 196, 0x17 }, \
1160 { 195, 0x0c }, \
1161 { 196, 0x06 }, \
1162 { 195, 0x0d }, \
1163 { 196, 0x09 }, \
1164 { 195, 0x0e }, \
1165 { 196, 0x05 }, \
1166 { 195, 0x0f }, \
1167 { 196, 0x09 }, \
1168 { 195, 0x10 }, \
1169 { 196, 0x20 }, \
1170 { 195, 0x20 }, \
1171 { 196, 0x17 }, \
1172 { 195, 0x21 }, \
1173 { 196, 0x06 }, \
1174 { 195, 0x22 }, \
1175 { 196, 0x09 }, \
1176 { 195, 0x23 }, \
1177 { 196, 0x17 }, \
1178 { 195, 0x24 }, \
1179 { 196, 0x06 }, \
1180 { 195, 0x25 }, \
1181 { 196, 0x09 }, \
1182 { 195, 0x26 }, \
1183 { 196, 0x17 }, \
1184 { 195, 0x27 }, \
1185 { 196, 0x06 }, \
1186 { 195, 0x28 }, \
1187 { 196, 0x09 }, \
1188 { 195, 0x29 }, \
1189 { 196, 0x05 }, \
1190 { 195, 0x2a }, \
1191 { 196, 0x09 }, \
1192 { 195, 0x80 }, \
1193 { 196, 0x8b }, \
1194 { 195, 0x81 }, \
1195 { 196, 0x12 }, \
1196 { 195, 0x82 }, \
1197 { 196, 0x09 }, \
1198 { 195, 0x83 }, \
1199 { 196, 0x17 }, \
1200 { 195, 0x84 }, \
1201 { 196, 0x11 }, \
1202 { 195, 0x85 }, \
1203 { 196, 0x00 }, \
1204 { 195, 0x86 }, \
1205 { 196, 0x00 }, \
1206 { 195, 0x87 }, \
1207 { 196, 0x18 }, \
1208 { 195, 0x88 }, \
1209 { 196, 0x60 }, \
1210 { 195, 0x89 }, \
1211 { 196, 0x44 }, \
1212 { 195, 0x8a }, \
1213 { 196, 0x8b }, \
1214 { 195, 0x8b }, \
1215 { 196, 0x8b }, \
1216 { 195, 0x8c }, \
1217 { 196, 0x8b }, \
1218 { 195, 0x8d }, \
1219 { 196, 0x8b }, \
1220 { 195, 0x8e }, \
1221 { 196, 0x09 }, \
1222 { 195, 0x8f }, \
1223 { 196, 0x09 }, \
1224 { 195, 0x90 }, \
1225 { 196, 0x09 }, \
1226 { 195, 0x91 }, \
1227 { 196, 0x09 }, \
1228 { 195, 0x92 }, \
1229 { 196, 0x11 }, \
1230 { 195, 0x93 }, \
1231 { 196, 0x11 }, \
1232 { 195, 0x94 }, \
1233 { 196, 0x11 }, \
1234 { 195, 0x95 }, \
1235 { 196, 0x11 }, \
1236 { 47, 0x80 }, \
1237 { 60, 0x80 }, \
1238 { 150, 0xd2 }, \
1239 { 151, 0x32 }, \
1240 { 152, 0x23 }, \
1241 { 153, 0x41 }, \
1242 { 154, 0x00 }, \
1243 { 155, 0x4f }, \
1244 { 253, 0x7e }, \
1245 { 195, 0x30 }, \
1246 { 196, 0x32 }, \
1247 { 195, 0x31 }, \
1248 { 196, 0x23 }, \
1249 { 195, 0x32 }, \
1250 { 196, 0x45 }, \
1251 { 195, 0x35 }, \
1252 { 196, 0x4a }, \
1253 { 195, 0x36 }, \
1254 { 196, 0x5a }, \
1255 { 195, 0x37 }, \
1256 { 196, 0x5a }
1262 { 0, 0x02 }, \
1263 { 1, 0x01 }, \
1264 { 2, 0x11 }, \
1265 { 3, 0xff }, \
1266 { 4, 0x0a }, \
1267 { 5, 0x20 }, \
1268 { 6, 0x00 }, \
1269 { 7, 0x00 }, \
1270 { 8, 0x00 }, \
1271 { 9, 0x00 }, \
1272 { 10, 0x00 }, \
1273 { 11, 0x21 }, \
1274 { 13, 0x00 }, \
1275 { 14, 0x7c }, \
1276 { 15, 0x22 }, \
1277 { 16, 0x80 }, \
1278 { 17, 0x99 }, \
1279 { 18, 0x99 }, \
1280 { 19, 0x09 }, \
1281 { 20, 0x50 }, \
1282 { 21, 0xb0 }, \
1283 { 22, 0x00 }, \
1284 { 23, 0xc5 }, \
1285 { 24, 0xfc }, \
1286 { 25, 0x40 }, \
1287 { 26, 0x4d }, \
1288 { 27, 0x02 }, \
1289 { 28, 0x72 }, \
1290 { 29, 0x01 }, \
1291 { 30, 0x00 }, \
1292 { 31, 0x00 }, \
1293 { 32, 0x00 }, \
1294 { 33, 0x00 }, \
1295 { 34, 0x23 }, \
1296 { 35, 0x01 }, \
1297 { 36, 0x00 }, \
1298 { 37, 0x00 }, \
1299 { 38, 0x00 }, \
1300 { 39, 0x20 }, \
1301 { 40, 0x00 }, \
1302 { 41, 0xd0 }, \
1303 { 42, 0x1b }, \
1304 { 43, 0x02 }, \
1305 { 44, 0x00 }
1308 { 0, 0x01 }, \
1309 { 1, 0x00 }, \
1310 { 2, 0x00 }, \
1311 { 3, 0x00 }, \
1312 { 4, 0x00 }, \
1313 { 5, 0x08 }, \
1314 { 6, 0x00 }, \
1315 { 7, 0x5b }, \
1316 { 8, 0x52 }, \
1317 { 9, 0xb6 }, \
1318 { 10, 0x57 }, \
1319 { 11, 0x33 }, \
1320 { 12, 0x22 }, \
1321 { 13, 0x3d }, \
1322 { 14, 0x3e }, \
1323 { 15, 0x13 }, \
1324 { 16, 0x22 }, \
1325 { 17, 0x23 }, \
1326 { 18, 0x02 }, \
1327 { 19, 0xa4 }, \
1328 { 20, 0x01 }, \
1329 { 21, 0x12 }, \
1330 { 22, 0x80 }, \
1331 { 23, 0xb3 }, \
1332 { 24, 0x00 }, \
1333 { 25, 0x00 }, \
1334 { 26, 0x00 }, \
1335 { 27, 0x00 }, \
1336 { 28, 0x18 }, \
1337 { 29, 0xee }, \
1338 { 30, 0x6b }, \
1339 { 31, 0x31 }, \
1340 { 32, 0x5d }, \
1341 { 33, 0x00 }, \
1342 { 34, 0x96 }, \
1343 { 35, 0x55 }, \
1344 { 36, 0x08 }, \
1345 { 37, 0xbb }, \
1346 { 38, 0xb3 }, \
1347 { 39, 0xb3 }, \
1348 { 40, 0x03 }, \
1349 { 41, 0x00 }, \
1350 { 42, 0x00 }, \
1351 { 43, 0xc5 }, \
1352 { 44, 0xc5 }, \
1353 { 45, 0xc5 }, \
1354 { 46, 0x07 }, \
1355 { 47, 0xa8 }, \
1356 { 48, 0xef }, \
1357 { 49, 0x1a }, \
1358 { 54, 0x07 }, \
1359 { 55, 0xa7 }, \
1360 { 56, 0xcc }, \
1361 { 57, 0x14 }, \
1362 { 58, 0x07 }, \
1363 { 59, 0xa8 }, \
1364 { 60, 0xd7 }, \
1365 { 61, 0x10 }, \
1366 { 62, 0x1c }, \
1367 { 63, 0x00 }
1370 { 0, 0x47 }, \
1371 { 1, 0x00 }, \
1372 { 2, 0x00 }, \
1373 { 3, 0x08 }, \
1374 { 4, 0x04 }, \
1375 { 5, 0x20 }, \
1376 { 6, 0x3a }, \
1377 { 7, 0x3a }, \
1378 { 8, 0x00 }, \
1379 { 9, 0x00 }, \
1380 { 10, 0x10 }, \
1381 { 11, 0x10 }, \
1382 { 12, 0x10 }, \
1383 { 13, 0x10 }, \
1384 { 14, 0x10 }, \
1385 { 15, 0x20 }, \
1386 { 16, 0x22 }, \
1387 { 17, 0x7c }, \
1388 { 18, 0x00 }, \
1389 { 19, 0x00 }, \
1390 { 20, 0x00 }, \
1391 { 21, 0xf1 }, \
1392 { 22, 0x11 }, \
1393 { 23, 0x02 }, \
1394 { 24, 0x41 }, \
1395 { 25, 0x20 }, \
1396 { 26, 0x00 }, \
1397 { 27, 0xd7 }, \
1398 { 28, 0xa2 }, \
1399 { 29, 0x20 }, \
1400 { 30, 0x49 }, \
1401 { 31, 0x20 }, \
1402 { 32, 0x04 }, \
1403 { 33, 0xf1 }, \
1404 { 34, 0xa1 }, \
1405 { 35, 0x01 }, \
1406 { 41, 0x00 }, \
1407 { 42, 0x00 }, \
1408 { 43, 0x00 }, \
1409 { 44, 0x00 }, \
1410 { 45, 0x00 }, \
1411 { 46, 0x00 }, \
1412 { 47, 0x00 }, \
1413 { 48, 0x00 }, \
1414 { 49, 0x00 }, \
1415 { 50, 0x00 }, \
1416 { 51, 0x00 }, \
1417 { 52, 0x00 }, \
1418 { 53, 0x00 }, \
1419 { 54, 0x00 }, \
1420 { 55, 0x00 }, \
1421 { 56, 0x00 }, \
1422 { 57, 0x00 }, \
1423 { 58, 0x31 }, \
1424 { 59, 0x31 }, \
1425 { 60, 0x0a }, \
1426 { 61, 0x02 }, \
1427 { 62, 0x00 }, \
1428 { 63, 0x00 }