Lines Matching +full:0 +full:x0900
37 #define MCS7840_RDREQ 0x0d
38 #define MCS7840_WRREQ 0x0e
41 #define MCS7840_EEPROM_RW_WVALUE 0x0900
47 #define MCS7840_DEV_REG_SP1 0x00 /* Options for UART 1, R/W */
48 #define MCS7840_DEV_REG_CONTROL1 0x01 /* Control bits for UART 1,
50 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong
52 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong
55 #define MCS7840_DEV_REG_GPIO 0x07 /* GPIO_0 and GPIO_1 bits,
58 #define MCS7840_DEV_REG_SP2 0x08 /* Options for UART 2, R/W */
59 #define MCS7840_DEV_REG_CONTROL2 0x09 /* Control bits for UART 2,
61 #define MCS7840_DEV_REG_SP3 0x0a /* Options for UART 3, R/W */
62 #define MCS7840_DEV_REG_CONTROL3 0x0b /* Control bits for UART 3,
64 #define MCS7840_DEV_REG_SP4 0x0c /* Options for UART 4, R/W */
65 #define MCS7840_DEV_REG_CONTROL4 0x0d /* Control bits for UART 4,
67 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */
68 #define MCS7840_DEV_REG_UNKNOWN1 0x0f /* NOT MENTIONED AND NOT USED */
69 #define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */
70 #define MCS7840_DEV_REG_CLOCK_MUX 0x12 /* PLL input clock & Interrupt
72 #define MCS7840_DEV_REG_UNKNOWN2 0x11 /* NOT MENTIONED AND NOT USED */
73 #define MCS7840_DEV_REG_CLOCK_SELECT12 0x13 /* Clock source for ports 1 &
75 #define MCS7840_DEV_REG_CLOCK_SELECT34 0x14 /* Clock source for ports 3 &
77 #define MCS7840_DEV_REG_UNKNOWN3 0x15 /* NOT MENTIONED AND NOT USED */
79 #define MCS7840_DEV_REG_UNKNOWN4 0x1f /* NOT MENTIONED AND NOT USED */
80 #define MCS7840_DEV_REG_UNKNOWN5 0x20 /* NOT MENTIONED AND NOT USED */
81 #define MCS7840_DEV_REG_UNKNOWN6 0x21 /* NOT MENTIONED AND NOT USED */
82 #define MCS7840_DEV_REG_UNKNOWN7 0x22 /* NOT MENTIONED AND NOT USED */
83 #define MCS7840_DEV_REG_UNKNOWN8 0x23 /* NOT MENTIONED AND NOT USED */
84 #define MCS7840_DEV_REG_UNKNOWN9 0x24 /* NOT MENTIONED AND NOT USED */
85 #define MCS7840_DEV_REG_UNKNOWNA 0x25 /* NOT MENTIONED AND NOT USED */
86 #define MCS7840_DEV_REG_UNKNOWNB 0x26 /* NOT MENTIONED AND NOT USED */
87 #define MCS7840_DEV_REG_UNKNOWNC 0x27 /* NOT MENTIONED AND NOT USED */
88 #define MCS7840_DEV_REG_UNKNOWND 0x28 /* NOT MENTIONED AND NOT USED */
89 #define MCS7840_DEV_REG_UNKNOWNE 0x29 /* NOT MENTIONED AND NOT USED */
90 #define MCS7840_DEV_REG_UNKNOWNF 0x2a /* NOT MENTIONED AND NOT USED */
91 #define MCS7840_DEV_REG_MODE 0x2b /* Hardware configuration,
93 #define MCS7840_DEV_REG_SP1_ICG 0x2c /* Inter character gap
96 #define MCS7840_DEV_REG_SP2_ICG 0x2d /* Inter character gap
99 #define MCS7840_DEV_REG_SP3_ICG 0x2e /* Inter character gap
102 #define MCS7840_DEV_REG_SP4_ICG 0x2f /* Inter character gap
105 #define MCS7840_DEV_REG_RX_SAMPLING12 0x30 /* RX sampling for ports 1 &
107 #define MCS7840_DEV_REG_RX_SAMPLING34 0x31 /* RX sampling for ports 3 &
109 #define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port
112 #define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port
115 #define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port
118 #define MCS7840_DEV_REG_BO_FIFO_STAT2 0x35 /* Bulk-out FIFO Stat for Port
121 #define MCS7840_DEV_REG_BI_FIFO_STAT3 0x36 /* Bulk-In FIFO Stat for Port
124 #define MCS7840_DEV_REG_BO_FIFO_STAT3 0x37 /* Bulk-out FIFO Stat for Port
127 #define MCS7840_DEV_REG_BI_FIFO_STAT4 0x38 /* Bulk-In FIFO Stat for Port
130 #define MCS7840_DEV_REG_BO_FIFO_STAT4 0x39 /* Bulk-out FIFO Stat for Port
133 #define MCS7840_DEV_REG_ZERO_PERIOD1 0x3a /* Period between zero out
135 #define MCS7840_DEV_REG_ZERO_PERIOD2 0x3b /* Period between zero out
137 #define MCS7840_DEV_REG_ZERO_PERIOD3 0x3c /* Period between zero out
139 #define MCS7840_DEV_REG_ZERO_PERIOD4 0x3d /* Period between zero out
141 #define MCS7840_DEV_REG_ZERO_ENABLE 0x3e /* Enable/disable of zero out
143 #define MCS7840_DEV_REG_THR_VAL_LOW1 0x3f /* Low 8 bits of threshold
146 #define MCS7840_DEV_REG_THR_VAL_HIGH1 0x40 /* High 1 bit of threshold
149 #define MCS7840_DEV_REG_THR_VAL_LOW2 0x41 /* Low 8 bits of threshold
152 #define MCS7840_DEV_REG_THR_VAL_HIGH2 0x42 /* High 1 bit of threshold
155 #define MCS7840_DEV_REG_THR_VAL_LOW3 0x43 /* Low 8 bits of threshold
158 #define MCS7840_DEV_REG_THR_VAL_HIGH3 0x44 /* High 1 bit of threshold
161 #define MCS7840_DEV_REG_THR_VAL_LOW4 0x45 /* Low 8 bits of threshold
164 #define MCS7840_DEV_REG_THR_VAL_HIGH4 0x46 /* High 1 bit of threshold
169 #define MCS7840_DEV_SPx_LOOP_PIPES 0x01 /* Loop Bulk-Out FIFO to the
170 * Bulk-In FIFO, default = 0 */
171 #define MCS7840_DEV_SPx_SKIP_ERR_DATA 0x02 /* Drop data bytes from UART,
173 * errors, default = 0 */
174 #define MCS7840_DEV_SPx_RESET_OUT_FIFO 0x04 /* Reset Bulk-Out FIFO */
175 #define MCS7840_DEV_SPx_RESET_IN_FIFO 0x08 /* Reset Bulk-In FIFO */
176 #define MCS7840_DEV_SPx_CLOCK_MASK 0x70 /* Mask to extract Baud CLK
178 #define MCS7840_DEV_SPx_CLOCK_X1 0x00 /* CLK = 1.8432Mhz, max speed
180 #define MCS7840_DEV_SPx_CLOCK_X2 0x10 /* CLK = 3.6864Mhz, max speed
182 #define MCS7840_DEV_SPx_CLOCK_X35 0x20 /* CLK = 6.4512Mhz, max speed
184 #define MCS7840_DEV_SPx_CLOCK_X4 0x30 /* CLK = 7.3728Mhz, max speed
186 #define MCS7840_DEV_SPx_CLOCK_X7 0x40 /* CLK = 12.9024Mhz, max speed
188 #define MCS7840_DEV_SPx_CLOCK_X8 0x50 /* CLK = 14.7456Mhz, max speed
190 #define MCS7840_DEV_SPx_CLOCK_24MHZ 0x60 /* CLK = 24.0000Mhz, max speed
192 #define MCS7840_DEV_SPx_CLOCK_48MHZ 0x70 /* CLK = 48.0000Mhz, max speed
194 #define MCS7840_DEV_SPx_CLOCK_SHIFT 4 /* Value 0..7 can be shifted
196 #define MCS7840_DEV_SPx_UART_RESET 0x80 /* Reset UART */
199 #define MCS7840_DEV_CONTROLx_HWFC 0x01 /* Enable hardware flow
203 * default = 0 */
204 #define MCS7840_DEV_CONTROLx_UNUNSED1 0x02 /* Reserved */
205 #define MCS7840_DEV_CONTROLx_CTS_ENABLE 0x04 /* CTS changes are
207 * default = 0 */
208 #define MCS7840_DEV_CONTROLx_UNUSED2 0x08 /* Reserved for ports
210 #define MCS7840_DEV_CONTROL1_DRIVER_DONE 0x08 /* USB enumerating is
214 #define MCS7840_DEV_CONTROLx_RX_NEGATE 0x10 /* Negate RX input,
216 * only, default = 0 */
217 #define MCS7840_DEV_CONTROLx_RX_DISABLE 0x20 /* Disable RX logic,
220 * default = 0 */
221 #define MCS7840_DEV_CONTROLx_FSM_CONTROL 0x40 /* Disable RX FSM when
224 * only, default = 0 */
225 #define MCS7840_DEV_CONTROLx_UNUSED3 0x80 /* Reserved */
243 * authors as "number of port" indicator, grounded (0) for two-port
246 #define MCS7840_DEV_GPIO_4PORTS 0x01 /* Device has 4 ports
248 #define MCS7840_DEV_GPIO_GPIO_0 0x01 /* The same as above */
249 #define MCS7840_DEV_GPIO_GPIO_1 0x02 /* GPIO_1 data */
259 #define MCS7840_DEV_PLL_DIV_M_MASK 0x3f /* Mask for M divider */
260 #define MCS7840_DEV_PLL_DIV_M_MIN 1 /* Minimum value for M, 0 is
266 #define MCS7840_DEV_PLL_DIV_N_MASK 0x3f /* Mask for N divider */
267 #define MCS7840_DEV_PLL_DIV_N_MIN 1 /* Minimum value for N, 0 is
273 #define MCS7840_DEV_CLOCK_MUX_INPUTMASK 0x03 /* Mask to extract PLL clock
275 #define MCS7840_DEV_CLOCK_MUX_IN12MHZ 0x00 /* 12Mhz PLL input, default */
276 #define MCS7840_DEV_CLOCK_MUX_INEXTRN 0x01 /* External (device-depended)
278 #define MCS7840_DEV_CLOCK_MUX_INRSV1 0x02 /* Reserved */
279 #define MCS7840_DEV_CLOCK_MUX_INRSV2 0x03 /* Reserved */
280 #define MCS7840_DEV_CLOCK_MUX_PLLHIGH 0x04 /* 0 = PLL Output is
283 #define MCS7840_DEV_CLOCK_MUX_INTRFIFOS 0x08 /* Enable additional 8 bytes
286 * = 0 */
287 #define MCS7840_DEV_CLOCK_MUX_RESERVED1 0x10 /* Unused */
288 #define MCS7840_DEV_CLOCK_MUX_RESERVED2 0x20 /* Unused */
289 #define MCS7840_DEV_CLOCK_MUX_RESERVED3 0x40 /* Unused */
290 #define MCS7840_DEV_CLOCK_MUX_RESERVED4 0x80 /* Unused */
293 #define MCS7840_DEV_CLOCK_SELECT1_MASK 0x07 /* Bits for port 1 in
295 #define MCS7840_DEV_CLOCK_SELECT1_SHIFT 0 /* Shift for port 1in
297 #define MCS7840_DEV_CLOCK_SELECT2_MASK 0x38 /* Bits for port 2 in
301 #define MCS7840_DEV_CLOCK_SELECT3_MASK 0x07 /* Bits for port 3 in
303 #define MCS7840_DEV_CLOCK_SELECT3_SHIFT 0 /* Shift for port 3 in
305 #define MCS7840_DEV_CLOCK_SELECT4_MASK 0x38 /* Bits for port 4 in
309 #define MCS7840_DEV_CLOCK_SELECT_STD 0x00 /* STANDARD baudrate derived
312 #define MCS7840_DEV_CLOCK_SELECT_30MHZ 0x01 /* 30Mhz */
313 #define MCS7840_DEV_CLOCK_SELECT_96MHZ 0x02 /* 96Mhz direct */
314 #define MCS7840_DEV_CLOCK_SELECT_120MHZ 0x03 /* 120Mhz */
315 #define MCS7840_DEV_CLOCK_SELECT_PLL 0x04 /* PLL output (see for M and N
317 #define MCS7840_DEV_CLOCK_SELECT_EXT 0x05 /* External clock input
319 #define MCS7840_DEV_CLOCK_SELECT_RES1 0x06 /* Unused */
320 #define MCS7840_DEV_CLOCK_SELECT_RES2 0x07 /* Unused */
323 #define MCS7840_DEV_MODE_RESERVED1 0x01 /* Unused */
324 #define MCS7840_DEV_MODE_RESET 0x02 /* 0: RESET = Active High
326 #define MCS7840_DEV_MODE_SER_PRSNT 0x04 /* 0: Reserved, 1: Do not use
329 #define MCS7840_DEV_MODE_PLLBYPASS 0x08 /* 1: PLL output is bypassed,
330 * default = 0 */
331 #define MCS7840_DEV_MODE_PORBYPASS 0x10 /* 1: Power-On Reset is
332 * bypassed, default = 0 */
333 #define MCS7840_DEV_MODE_SELECT24S 0x20 /* 0: 4 Serial Ports / IrDA
336 #define MCS7840_DEV_MODE_EEPROMWR 0x40 /* EEPROM write is enabled,
338 #define MCS7840_DEV_MODE_IRDA 0x80 /* IrDA mode is activated
343 #define MCS7840_DEV_SPx_ICG_DEF 0x24 /* All 8 bits is used as
351 * 0 is very beginning of period, 15 is very end, 7 is the middle.
353 #define MCS7840_DEV_RX_SAMPLING1_MASK 0x0f /* Bits for port 1 in
355 #define MCS7840_DEV_RX_SAMPLING1_SHIFT 0 /* Shift for port 1in
357 #define MCS7840_DEV_RX_SAMPLING2_MASK 0xf0 /* Bits for port 2 in
361 #define MCS7840_DEV_RX_SAMPLING3_MASK 0x0f /* Bits for port 3 in
363 #define MCS7840_DEV_RX_SAMPLING3_SHIFT 0 /* Shift for port 3 in
365 #define MCS7840_DEV_RX_SAMPLING4_MASK 0xf0 /* Bits for port 4 in
369 #define MCS7840_DEV_RX_SAMPLINGx_MIN 0 /* Max for any RX Sampling */
380 #define MCS7840_DEV_ZERO_ENABLE_PORT1 0x01 /* Enable of sending
383 #define MCS7840_DEV_ZERO_ENABLE_PORT2 0x02 /* Enable of sending
386 #define MCS7840_DEV_ZERO_ENABLE_PORT3 0x04 /* Enable of sending
389 #define MCS7840_DEV_ZERO_ENABLE_PORT4 0x08 /* Enable of sending
394 #define MCS7840_DEV_THR_VAL_HIGH_MASK 0x01 /* Only one bit is used */
397 #define MCS7840_DEV_THR_VAL_HIGH_ENABLE 0x80 /* Enable threshold */
400 #define MCS7840_DEV_REG_DCR0_1 0x04 /* Device contol register 0 for Port
402 #define MCS7840_DEV_REG_DCR1_1 0x05 /* Device contol register 1 for Port
404 #define MCS7840_DEV_REG_DCR2_1 0x06 /* Device contol register 2 for Port
406 #define MCS7840_DEV_REG_DCR0_2 0x16 /* Device contol register 0 for Port
408 #define MCS7840_DEV_REG_DCR1_2 0x17 /* Device contol register 1 for Port
410 #define MCS7840_DEV_REG_DCR2_2 0x18 /* Device contol register 2 for Port
412 #define MCS7840_DEV_REG_DCR0_3 0x19 /* Device contol register 0 for Port
414 #define MCS7840_DEV_REG_DCR1_3 0x1a /* Device contol register 1 for Port
416 #define MCS7840_DEV_REG_DCR2_3 0x1b /* Device contol register 2 for Port
418 #define MCS7840_DEV_REG_DCR0_4 0x1c /* Device contol register 0 for Port
420 #define MCS7840_DEV_REG_DCR1_4 0x1d /* Device contol register 1 for Port
422 #define MCS7840_DEV_REG_DCR2_4 0x1e /* Device contol register 2 for Port
426 #define MCS7840_DEV_DCR0_PWRSAVE 0x01 /* Shutdown transiver
429 #define MCS7840_DEV_DCR0_RESERVED1 0x02 /* Unused */
430 #define MCS7840_DEV_DCR0_GPIO_MODE_MASK 0x0c /* GPIO Mode bits, WORKS
432 #define MCS7840_DEV_DCR0_GPIO_MODE_IN 0x00 /* GPIO Mode - Input
433 * (0b00), WORKS ONLY
435 #define MCS7840_DEV_DCR0_GPIO_MODE_OUT 0x08 /* GPIO Mode - Input
436 * (0b10), WORKS ONLY
438 #define MCS7840_DEV_DCR0_RTS_ACTIVE_HIGH 0x10 /* RTS Active is HIGH,
439 * default = 0 (low) */
440 #define MCS7840_DEV_DCR0_RTS_AUTO 0x20 /* RTS is controlled by
442 * default = 0
444 #define MCS7840_DEV_DCR0_IRDA 0x40 /* IrDA mode */
445 #define MCS7840_DEV_DCR0_RESERVED2 0x80 /* Unused */
448 #define MCS7840_DEV_DCR1_GPIO_CURRENT_MASK 0x03 /* Mask to extract GPIO
451 #define MCS7840_DEV_DCR1_GPIO_CURRENT_6MA 0x00 /* GPIO output current
454 #define MCS7840_DEV_DCR1_GPIO_CURRENT_8MA 0x01 /* GPIO output current
457 #define MCS7840_DEV_DCR1_GPIO_CURRENT_10MA 0x02 /* GPIO output current
460 #define MCS7840_DEV_DCR1_GPIO_CURRENT_12MA 0x03 /* GPIO output current
463 #define MCS7840_DEV_DCR1_UART_CURRENT_MASK 0x0c /* Mask to extract UART
465 #define MCS7840_DEV_DCR1_UART_CURRENT_6MA 0x00 /* UART output current
467 #define MCS7840_DEV_DCR1_UART_CURRENT_8MA 0x04 /* UART output current
469 #define MCS7840_DEV_DCR1_UART_CURRENT_10MA 0x08 /* UART output current
471 #define MCS7840_DEV_DCR1_UART_CURRENT_12MA 0x0c /* UART output current
473 #define MCS7840_DEV_DCR1_WAKEUP_DISABLE 0x10 /* Disable Remote USB
475 #define MCS7840_DEV_DCR1_PLLPWRDOWN_DISABLE 0x20 /* Disable PLL power
478 #define MCS7840_DEV_DCR1_LONG_INTERRUPT 0x40 /* Enable 13 bytes of
482 #define MCS7840_DEV_DCR1_RESERVED1 0x80 /* Unused */
486 * Wakeup will work only if DCR0_IRDA = 0 (RS-xxx mode) and
487 * DCR1_WAKEUP_DISABLE = 0 (wakeup enabled).
489 #define MCS7840_DEV_DCR2_WAKEUP_CTS 0x01 /* Wakeup on CTS change,
490 * default = 0 */
491 #define MCS7840_DEV_DCR2_WAKEUP_DCD 0x02 /* Wakeup on DCD change,
492 * default = 0 */
493 #define MCS7840_DEV_DCR2_WAKEUP_RI 0x04 /* Wakeup on RI change,
495 #define MCS7840_DEV_DCR2_WAKEUP_DSR 0x08 /* Wakeup on DSR change,
496 * default = 0 */
497 #define MCS7840_DEV_DCR2_WAKEUP_RXD 0x10 /* Wakeup on RX Data change,
498 * default = 0 */
499 #define MCS7840_DEV_DCR2_WAKEUP_RESUME 0x20 /* Wakeup issues RESUME
502 #define MCS7840_DEV_DCR2_RESERVED1 0x40 /* Unused */
503 #define MCS7840_DEV_DCR2_SHDN_POLARITY 0x80 /* 0: Pin 12 Active Low, 1:
505 * = 0 */
513 #define MCS7840_IEP_BO_PORT1_HASDATA 0x01
514 #define MCS7840_IEP_BI_PORT1_HASDATA 0x02
515 #define MCS7840_IEP_BO_PORT2_HASDATA 0x04
516 #define MCS7840_IEP_BI_PORT2_HASDATA 0x08
517 #define MCS7840_IEP_BO_PORT3_HASDATA 0x10
518 #define MCS7840_IEP_BI_PORT3_HASDATA 0x20
519 #define MCS7840_IEP_BO_PORT4_HASDATA 0x40
520 #define MCS7840_IEP_BI_PORT4_HASDATA 0x80
523 #define MCS7840_UART_REG_THR 0x00 /* Transmitter Holding
525 #define MCS7840_UART_REG_RHR 0x00 /* Receiver Holding Register
527 #define MCS7840_UART_REG_IER 0x01 /* Interrupt enable register -
529 #define MCS7840_UART_REG_FCR 0x02 /* FIFO Control register -
531 #define MCS7840_UART_REG_ISR 0x02 /* Interrupt Status Registter
533 #define MCS7840_UART_REG_LCR 0x03 /* Line control register R/W */
534 #define MCS7840_UART_REG_MCR 0x04 /* Modem control register R/W */
535 #define MCS7840_UART_REG_LSR 0x05 /* Line status register R/Only */
536 #define MCS7840_UART_REG_MSR 0x06 /* Modem status register
538 #define MCS7840_UART_REG_SCRATCHPAD 0x07 /* Scratch pad register */
540 #define MCS7840_UART_REG_DLL 0x00 /* Low bits of BAUD divider */
541 #define MCS7840_UART_REG_DLM 0x01 /* High bits of BAUD divider */
544 #define MCS7840_UART_IER_RXREADY 0x01 /* RX Ready interrumpt mask */
545 #define MCS7840_UART_IER_TXREADY 0x02 /* TX Ready interrumpt mask */
546 #define MCS7840_UART_IER_RXSTAT 0x04 /* RX Status interrumpt mask */
547 #define MCS7840_UART_IER_MODEM 0x08 /* Modem status change
549 #define MCS7840_UART_IER_SLEEP 0x10 /* SLEEP enable */
552 #define MCS7840_UART_FCR_ENABLE 0x01 /* Enable FIFO */
553 #define MCS7840_UART_FCR_FLUSHRHR 0x02 /* Flush RHR and FIFO */
554 #define MCS7840_UART_FCR_FLUSHTHR 0x04 /* Flush THR and FIFO */
555 #define MCS7840_UART_FCR_RTLMASK 0xa0 /* Mask to select RHR
557 #define MCS7840_UART_FCR_RTL_1_1 0x00 /* L1 = 1, L2 = 1 */
558 #define MCS7840_UART_FCR_RTL_1_4 0x40 /* L1 = 1, L2 = 4 */
559 #define MCS7840_UART_FCR_RTL_1_8 0x80 /* L1 = 1, L2 = 8 */
560 #define MCS7840_UART_FCR_RTL_1_14 0xa0 /* L1 = 1, L2 = 14 */
563 #define MCS7840_UART_ISR_NOPENDING 0x01 /* No interrupt pending */
564 #define MCS7840_UART_ISR_INTMASK 0x3f /* Mask to select interrupt
566 #define MCS7840_UART_ISR_RXERR 0x06 /* Recevir error */
567 #define MCS7840_UART_ISR_RXHASDATA 0x04 /* Recevier has data */
568 #define MCS7840_UART_ISR_RXTIMEOUT 0x0c /* Recevier timeout */
569 #define MCS7840_UART_ISR_TXEMPTY 0x02 /* Transmitter empty */
570 #define MCS7840_UART_ISR_MSCHANGE 0x00 /* Modem status change */
573 #define MCS7840_UART_LCR_DATALENMASK 0x03 /* Mask for data length */
574 #define MCS7840_UART_LCR_DATALEN5 0x00 /* 5 data bits */
575 #define MCS7840_UART_LCR_DATALEN6 0x01 /* 6 data bits */
576 #define MCS7840_UART_LCR_DATALEN7 0x02 /* 7 data bits */
577 #define MCS7840_UART_LCR_DATALEN8 0x03 /* 8 data bits */
579 #define MCS7840_UART_LCR_STOPBMASK 0x04 /* Mask for stop bits */
580 #define MCS7840_UART_LCR_STOPB1 0x00 /* 1 stop bit in any case */
581 #define MCS7840_UART_LCR_STOPB2 0x04 /* 1.5-2 stop bits depends on
584 #define MCS7840_UART_LCR_PARITYMASK 0x38 /* Mask for all parity data */
585 #define MCS7840_UART_LCR_PARITYON 0x08 /* Parity ON/OFF - ON */
586 #define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */
587 #define MCS7840_UART_LCR_PARITYEVEN 0x10 /* Parity Even */
588 #define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */
589 #define MCS7840_UART_LCR_PARITYFORCE 0x20 /* Force parity odd/even */
591 #define MCS7840_UART_LCR_BREAK 0x40 /* Send BREAK */
592 #define MCS7840_UART_LCR_DIVISORS 0x80 /* Map DLL/DLM instead of
596 #define MCS7840_UART_LSR_RHRAVAIL 0x01 /* Data available for read */
597 #define MCS7840_UART_LSR_RHROVERRUN 0x02 /* Data FIFO/register overflow */
598 #define MCS7840_UART_LSR_PARITYERR 0x04 /* Parity error */
599 #define MCS7840_UART_LSR_FRAMEERR 0x10 /* Framing error */
600 #define MCS7840_UART_LSR_BREAKERR 0x20 /* BREAK signal received */
601 #define MCS7840_UART_LSR_THREMPTY 0x40 /* THR register is empty,
603 #define MCS7840_UART_LSR_HASERR 0x80 /* Has error in receiver FIFO */
606 #define MCS7840_UART_MCR_DTR 0x01 /* Force DTR to be active
608 #define MCS7840_UART_MCR_RTS 0x02 /* Force RTS to be active
610 #define MCS7840_UART_MCR_IE 0x04 /* Enable interrupts (from
612 #define MCS7840_UART_MCR_LOOPBACK 0x10 /* Enable local loopback test
614 #define MCS7840_UART_MCR_CTSRTS 0x20 /* Enable CTS/RTS flow control
616 #define MCS7840_UART_MCR_DTRDSR 0x40 /* Enable DTR/DSR flow control
618 #define MCS7840_UART_MCR_DCD 0x80 /* Enable DCD flow control in
622 #define MCS7840_UART_MSR_DELTACTS 0x01 /* CTS was changed since last
624 #define MCS7840_UART_MSR_DELTADSR 0x02 /* DSR was changed since last
626 #define MCS7840_UART_MSR_DELTARI 0x04 /* RI was changed from low to
628 #define MCS7840_UART_MSR_DELTADCD 0x08 /* DCD was changed since last
630 #define MCS7840_UART_MSR_NEGCTS 0x10 /* Negated CTS signal */
631 #define MCS7840_UART_MSR_NEGDSR 0x20 /* Negated DSR signal */
632 #define MCS7840_UART_MSR_NEGRI 0x40 /* Negated RI signal */
633 #define MCS7840_UART_MSR_NEGDCD 0x80 /* Negated DCD signal */
636 #define MCS7840_UART_SCRATCHPAD_RS232 0x00 /* RS-485 disabled */
637 #define MCS7840_UART_SCRATCHPAD_RS485_DTRRX 0x80 /* RS-485 mode, DTR High
639 #define MCS7840_UART_SCRATCHPAD_RS485_DTRTX 0xc0 /* RS-485 mode, DTR High
642 #define MCS7840_CONFIG_INDEX 0
643 #define MCS7840_IFACE_INDEX 0