Lines Matching +full:0 +full:x0040
30 #define URE_CONFIG_IDX 0 /* config number 1 */
31 #define URE_IFACE_IDX 0
33 #define URE_CTL_READ 0x01
34 #define URE_CTL_WRITE 0x02
39 #define URE_BYTE_EN_DWORD 0xff
40 #define URE_BYTE_EN_WORD 0x33
41 #define URE_BYTE_EN_BYTE 0x11
42 #define URE_BYTE_EN_SIX_BYTES 0x3f
49 #define URE_PLA_IDR 0xc000
50 #define URE_PLA_RCR 0xc010
51 #define URE_PLA_RMS 0xc016
52 #define URE_PLA_RXFIFO_CTRL0 0xc0a0
53 #define URE_PLA_RXFIFO_CTRL1 0xc0a4
54 #define URE_PLA_RXFIFO_CTRL2 0xc0a8
55 #define URE_PLA_DMY_REG0 0xc0b0
56 #define URE_PLA_FMC 0xc0b4
57 #define URE_PLA_CFG_WOL 0xc0b6
58 #define URE_PLA_TEREDO_CFG 0xc0bc
59 #define URE_PLA_MAR0 0xcd00
60 #define URE_PLA_MAR4 0xcd04
61 #define URE_PLA_BACKUP 0xd000
62 #define URE_PAL_BDC_CR 0xd1a0
63 #define URE_PLA_TEREDO_TIMER 0xd2cc
64 #define URE_PLA_REALWOW_TIMER 0xd2e8
65 #define URE_PLA_SUSPEND_FLAG 0xd38a
66 #define URE_PLA_INDICATE_FALG 0xd38c
67 #define URE_PLA_EXTRA_STATUS 0xd398
68 #define URE_PLA_LEDSEL 0xdd90
69 #define URE_PLA_LED_FEATURE 0xdd92
70 #define URE_PLA_PHYAR 0xde00
71 #define URE_PLA_BOOT_CTRL 0xe004
72 #define URE_PLA_GPHY_INTR_IMR 0xe022
73 #define URE_PLA_EEE_CR 0xe040
74 #define URE_PLA_EEEP_CR 0xe080
75 #define URE_PLA_MAC_PWR_CTRL 0xe0c0
76 #define URE_PLA_MAC_PWR_CTRL2 0xe0ca
77 #define URE_PLA_MAC_PWR_CTRL3 0xe0cc
78 #define URE_PLA_MAC_PWR_CTRL4 0xe0ce
79 #define URE_PLA_WDT6_CTRL 0xe428
80 #define URE_PLA_TCR0 0xe610
81 #define URE_PLA_TCR1 0xe612
82 #define URE_PLA_MTPS 0xe615
83 #define URE_PLA_TXFIFO_CTRL 0xe618
84 #define URE_PLA_RSTTALLY 0xe800
85 #define URE_PLA_CR 0xe813
86 #define URE_PLA_CRWECR 0xe81c
87 #define URE_PLA_CONFIG34 0xe820
88 #define URE_PLA_CONFIG5 0xe822
89 #define URE_PLA_PHY_PWR 0xe84c
90 #define URE_PLA_OOB_CTRL 0xe84f
91 #define URE_PLA_CPCR 0xe854
92 #define URE_PLA_MISC_0 0xe858
93 #define URE_PLA_MISC_1 0xe85a
94 #define URE_PLA_OCP_GPHY_BASE 0xe86c
95 #define URE_PLA_TELLYCNT 0xe890
96 #define URE_PLA_SFF_STS_7 0xe8de
97 #define URE_PLA_PHYSTATUS 0xe908
98 #define URE_GMEDIASTAT 0xe908
99 #define URE_PLA_BP_BA 0xfc26
100 #define URE_PLA_BP_0 0xfc28
101 #define URE_PLA_BP_1 0xfc2a
102 #define URE_PLA_BP_2 0xfc2c
103 #define URE_PLA_BP_3 0xfc2e
104 #define URE_PLA_BP_4 0xfc30
105 #define URE_PLA_BP_5 0xfc32
106 #define URE_PLA_BP_6 0xfc34
107 #define URE_PLA_BP_7 0xfc36
108 #define URE_PLA_BP_EN 0xfc38
110 #define URE_USB_USB2PHY 0xb41e
111 #define URE_USB_SSPHYLINK2 0xb428
112 #define URE_USB_U2P3_CTRL 0xb460
113 #define URE_USB_CSR_DUMMY1 0xb464
114 #define URE_USB_CSR_DUMMY2 0xb466
115 #define URE_USB_DEV_STAT 0xb808
116 #define URE_USB_CONNECT_TIMER 0xcbf8
117 #define URE_USB_MSC_TIMER 0xcbfc
118 #define URE_USB_BURST_SIZE 0xcfc0
119 #define URE_USB_LPM_CONFIG 0xcfd8
120 #define URE_USB_FW_CTRL 0xd334 /* RTL8153B */
121 #define URE_USB_USB_CTRL 0xd406
122 #define URE_USB_PHY_CTRL 0xd408
123 #define URE_USB_TX_AGG 0xd40a
124 #define URE_USB_RX_BUF_TH 0xd40c
125 #define URE_USB_FW_TASK 0xd4e8 /* RTL8153B */
126 #define URE_USB_USB_TIMER 0xd428
127 #define URE_USB_RX_EARLY_AGG 0xd42c
128 #define URE_USB_RX_EARLY_SIZE 0xd42e
129 #define URE_USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
130 #define URE_USB_RX_EXTRA_AGG_TMR 0xd432 /* RTL8153B */
131 #define URE_USB_TX_DMA 0xd434
132 #define URE_USB_UPT_RXDMA_OWN 0xd437
133 #define URE_USB_FC_TIMER 0xd340
134 #define URE_USB_TOLERANCE 0xd490
135 #define URE_USB_LPM_CTRL 0xd41a
136 #define URE_USB_BMU_RESET 0xd4b0
137 #define URE_USB_U1U2_TIMER 0xd4da
138 #define URE_USB_UPS_CTRL 0xd800
139 #define URE_USB_POWER_CUT 0xd80a
140 #define URE_USB_MISC_0 0xd81a
141 #define URE_USB_AFE_CTRL2 0xd824
142 #define URE_USB_WDT11_CTRL 0xe43c
153 #define URE_USB_BP_8 0xfc38 /* RTL8153B */
154 #define URE_USB_BP_9 0xfc3a
155 #define URE_USB_BP_10 0xfc3c
156 #define URE_USB_BP_11 0xfc3e
157 #define URE_USB_BP_12 0xfc40
158 #define URE_USB_BP_13 0xfc42
159 #define URE_USB_BP_14 0xfc44
160 #define URE_USB_BP_15 0xfc46
161 #define URE_USB_BP2_EN 0xfc48
165 #define URE_OCP_ALDPS_CONFIG 0x2010
166 #define URE_OCP_EEE_CONFIG1 0x2080
167 #define URE_OCP_EEE_CONFIG2 0x2092
168 #define URE_OCP_EEE_CONFIG3 0x2094
169 #define URE_OCP_BASE_MII 0xa400
170 #define URE_OCP_EEE_AR 0xa41a
171 #define URE_OCP_EEE_DATA 0xa41c
172 #define URE_OCP_PHY_STATUS 0xa420
173 #define URE_OCP_POWER_CFG 0xa430
174 #define URE_OCP_EEE_CFG 0xa432
175 #define URE_OCP_SRAM_ADDR 0xa436
176 #define URE_OCP_SRAM_DATA 0xa438
177 #define URE_OCP_DOWN_SPEED 0xa442
178 #define URE_OCP_EEE_ABLE 0xa5c4
179 #define URE_OCP_EEE_ADV 0xa5d0
180 #define URE_OCP_EEE_LPABLE 0xa5d2
181 #define URE_OCP_PHY_STATE 0xa708
182 #define URE_OCP_PHY_PATCH_STAT 0xb800
183 #define URE_OCP_PHY_PATCH_CMD 0xb820
184 #define URE_OCP_PHY_LOCK 0xb82e
185 #define URE_OCP_ADC_CFG 0xbc06
188 #define URE_SRAM_GREEN_CFG 0x8011
189 #define URE_SRAM_LPF_CFG 0x8012
190 #define URE_SRAM_GPHY_FW_VER 0x801e
191 #define URE_SRAM_10M_AMP1 0x8080
192 #define URE_SRAM_10M_AMP2 0x8082
193 #define URE_SRAM_IMPEDANCE 0x8084
194 #define URE_SRAM_PHY_LOCK 0xb82e
197 #define URE_RCR_AAP 0x00000001
198 #define URE_RCR_APM 0x00000002
199 #define URE_RCR_AM 0x00000004
200 #define URE_RCR_AB 0x00000008
201 #define URE_RCR_AR 0x00000010 /* runt */
202 #define URE_RCR_AER 0x00000020 /* error pkts */
203 #define URE_RCR_ACPTFLOW 0x00000080
204 #define URE_RCR_RXEMPTY 0x00020000
209 #define URE_RXFIFO_THR1_NORMAL 0x00080002
210 #define URE_RXFIFO_THR1_OOB 0x01800003
213 #define URE_RXFIFO_THR2_FULL 0x00000060
214 #define URE_RXFIFO_THR2_HIGH 0x00000038
215 #define URE_RXFIFO_THR2_OOB 0x0000004a
216 #define URE_RXFIFO_THR2_NORMAL 0x00a0
219 #define URE_RXFIFO_THR3_FULL 0x00000078
220 #define URE_RXFIFO_THR3_HIGH 0x00000048
221 #define URE_RXFIFO_THR3_OOB 0x0000005a
222 #define URE_RXFIFO_THR3_NORMAL 0x0110
225 #define URE_TXFIFO_THR_NORMAL 0x00400008
226 #define URE_TXFIFO_THR_NORMAL2 0x01000008
229 #define URE_ECM_ALDPS 0x0002
232 #define URE_FMC_FCR_MCU_EN 0x0001
235 #define URE_EEEP_CR_EEEP_TX 0x0002
238 #define URE_WDT6_SET_MODE 0x0010
241 #define URE_TCR0_TX_EMPTY 0x0800
242 #define URE_TCR0_AUTO_FIFO 0x0080
245 #define URE_VERSION_MASK 0x7cf0
252 #define URE_TALLY_RESET 0x0001
255 #define URE_CR_RST 0x10
256 #define URE_CR_RE 0x08
257 #define URE_CR_TE 0x04
260 #define URE_CRWECR_NORAML 0x00
261 #define URE_CRWECR_CONFIG 0xc0
264 #define URE_NOW_IS_OOB 0x80
265 #define URE_TXFIFO_EMPTY 0x20
266 #define URE_RXFIFO_EMPTY 0x10
267 #define URE_LINK_LIST_READY 0x02
268 #define URE_DIS_MCU_CLROOB 0x01
272 #define URE_RXDY_GATED_EN 0x0008
275 #define URE_RE_INIT_LL 0x8000
276 #define URE_MCU_BORW_EN 0x4000
279 #define URE_CPCR_RX_VLAN 0x0040
282 #define URE_TEREDO_SEL 0x8000
283 #define URE_TEREDO_WAKE_MASK 0x7f00
284 #define URE_TEREDO_RS_EVENT_MASK 0x00fe
285 #define URE_OOB_TEREDO_EN 0x0001
288 #define URE_ALDPS_PROXY_MODE 0x0001
291 #define URE_LINK_OFF_WAKE_EN 0x0008
292 #define URE_LINK_ON_WAKE_EN 0x0010
295 #define URE_LAN_WAKE_EN 0x0002
298 #define URE_LED_MODE_MASK 0x0700
301 #define URE_TX_10M_IDLE_EN 0x0080
302 #define URE_PFM_PWM_SWITCH 0x0040
305 #define URE_D3_CLK_GATED_EN 0x00004000
306 #define URE_MCU_CLK_RATIO 0x07010f07
307 #define URE_MCU_CLK_RATIO_MASK 0x0f0f0f0f
308 #define URE_ALDPS_SPDWN_RATIO 0x0f87
311 #define URE_MAC_CLK_SPDWN_EN 0x8000
312 #define URE_EEE_SPDWN_RATIO 0x8007
315 #define URE_PLA_MCU_SPDWN_EN 0x4000
316 #define URE_PKT_AVAIL_SPDWN_EN 0x0100
317 #define URE_SUSPEND_SPDWN_EN 0x0004
318 #define URE_U1U2_SPDWN_EN 0x0002
319 #define URE_L1_SPDWN_EN 0x0001
322 #define URE_PWRSAVE_SPDWN_EN 0x1000
323 #define URE_RXDV_SPDWN_EN 0x0800
324 #define URE_TX10MIDLE_EN 0x0100
325 #define URE_TP100_SPDWN_EN 0x0020
326 #define URE_TP500_SPDWN_EN 0x0010
327 #define URE_TP1000_SPDWN_EN 0x0008
328 #define URE_EEE_SPDWN_EN 0x0001
331 #define URE_GPHY_STS_MSK 0x0001
332 #define URE_SPEED_DOWN_MSK 0x0002
333 #define URE_SPDWN_RXDV_MSK 0x0004
334 #define URE_SPDWN_LINKCHG_MSK 0x0008
337 #define URE_PHYAR_PHYDATA 0x0000ffff
338 #define URE_PHYAR_BUSY 0x80000000
341 #define URE_EEE_RX_EN 0x0001
342 #define URE_EEE_TX_EN 0x0002
345 #define URE_AUTOLOAD_DONE 0x0002
348 #define URE_LINK_CHG_EVENT 0x01
351 #define URE_UPCOMING_RUNTIME_D3 0x01
354 #define URE_POLL_LINK_CHG 0x0001
355 #define URE_LINK_CHANGE_FLAG 0x0100
356 #define URE_CUR_LINK_OK 0x8000
359 #define URE_PHYSTATUS_FDX 0x0001
360 #define URE_PHYSTATUS_LINK 0x0002
361 #define URE_PHYSTATUS_10MBPS 0x0004
362 #define URE_PHYSTATUS_100MBPS 0x0008
363 #define URE_PHYSTATUS_1000MBPS 0x0010
364 #define URE_PHYSTATUS_500MBPS 0x0100
365 #define URE_PHYSTATUS_1250MBPS 0x0200
366 #define URE_PHYSTATUS_2500MBPS 0x0400
369 #define URE_USB2PHY_SUSPEND 0x0001
370 #define URE_USB2PHY_L1 0x0002
373 #define URE_PWD_DN_SCALE_MASK 0x3ffe
377 #define URE_DYNAMIC_BURST 0x0001
380 #define URE_EP4_FULL_FC 0x0001
383 #define URE_STAT_SPEED_MASK 0x0006
384 #define URE_STAT_SPEED_HIGH 0x0000
385 #define URE_STAT_SPEED_FULL 0x0001
388 #define URE_LPM_U1U2_EN 0x0001
391 #define URE_TX_AGG_MAX_THRESHOLD 0x03
394 #define URE_RX_THR_SUPER 0x0c350180
395 #define URE_RX_THR_HIGH 0x7a120180
396 #define URE_RX_THR_SLOW 0xffff0180
397 #define URE_RX_THR_B 0x00010001
400 #define URE_TEST_MODE_DISABLE 0x00000001
401 #define URE_TX_SIZE_ADJUST1 0x00000100
404 #define URE_BMU_RESET_EP_IN 0x01
405 #define URE_BMU_RESET_EP_OUT 0x02
408 #define URE_OWN_UPDATE 0x01
409 #define URE_OWN_CLEAR 0x02
412 #define URE_FC_PATCH_TASK 0x0001
415 #define URE_POWER_CUT 0x0100
418 #define URE_RESUME_INDICATE 0x0001
421 #define URE_FLOW_CTRL_PATCH_OPT 0x01
424 #define URE_CTRL_TIMER_EN 0x8000
427 #define URE_RX_AGG_DISABLE 0x0010
428 #define URE_RX_ZERO_EN 0x0080
431 #define URE_U2P3_ENABLE 0x0001
434 #define URE_PWR_EN 0x0001
435 #define URE_PHASE2_EN 0x0008
436 #define URE_UPS_EN 0x0010
437 #define URE_USP_PREWAKE 0x0020
440 #define URE_PCUT_STATUS 0x0001
448 #define URE_TIMER11_EN 0x0001
451 #define URE_FIFO_EMPTY_1FB 0x30
452 #define URE_LPM_TIMER_MASK 0x0c
453 #define URE_LPM_TIMER_500MS 0x04
454 #define URE_LPM_TIMER_500US 0x0c
455 #define URE_ROK_EXIT_LPM 0x02
458 #define URE_SEN_VAL_MASK 0xf800
459 #define URE_SEN_VAL_NORMAL 0xa000
460 #define URE_SEL_RXIDLE 0x0100
463 #define URE_ENPWRSAVE 0x8000
464 #define URE_ENPDNPS 0x0200
465 #define URE_LINKENA 0x0100
466 #define URE_DIS_SDSAVE 0x0010
469 #define URE_PHY_STAT_MASK 0x0007
475 #define URE_EEE_CLKDIV_EN 0x8000
476 #define URE_EN_ALDPS 0x0004
477 #define URE_EN_10M_PLLOFF 0x0001
480 #define URE_CTAP_SHORT_EN 0x0040
481 #define URE_EEE10_EN 0x0010
484 #define URE_EN_10M_BGOFF 0x0080
485 #define URE_EN_10M_CLKDIV 0x0800
486 #define URE_EN_EEE_100 0x1000
487 #define URE_EN_EEE_1000 0x2000
488 #define URE_EN_EEE_CMODE 0x4000
491 #define URE_TXDIS_STATE 0x01
492 #define URE_ABD_STATE 0x02
495 #define URE_PATCH_READY 0x40
498 #define URE_PATCH_REQUEST 0x10
501 #define URE_PATCH_LOCK 0x01
504 #define URE_CKADSEL_L 0x0100
505 #define URE_ADC_EN 0x0080
506 #define URE_EN_EMI_L 0x0040
509 #define URE_GREEN_ETH_EN 0x8000
512 #define URE_PHY_PATCH_LOCK 0x0001
514 #define URE_ADV_2500TFDX 0x0080
516 #define URE_MCU_TYPE_PLA 0x0100
517 #define URE_MCU_TYPE_USB 0x0000
535 #define URE_RXPKT_LEN_MASK 0x7fff
538 #define URE_RXPKT_VLAN_MASK 0xffff
558 #define URE_TXPKT_LEN_MASK 0xffff
560 #define URE_L4_OFFSET_MAX 0x7ff
562 #define URE_TXPKT_VLAN_MASK 0xffff
593 #define URE_FLAG_LINK 0x0001
594 #define URE_FLAG_8152 0x0100 /* RTL8152 */
595 #define URE_FLAG_8153 0x0200 /* RTL8153 */
596 #define URE_FLAG_8153B 0x0400 /* RTL8153B */
597 #define URE_FLAG_8156 0x0800 /* RTL8156 */
598 #define URE_FLAG_8156B 0x1000 /* RTL8156B */
602 #define URE_CHIP_VER_4C00 0x0001
603 #define URE_CHIP_VER_4C10 0x0002
604 #define URE_CHIP_VER_5C00 0x0004
605 #define URE_CHIP_VER_5C10 0x0008
606 #define URE_CHIP_VER_5C20 0x0010
607 #define URE_CHIP_VER_5C30 0x0020
608 #define URE_CHIP_VER_6000 0x0040
609 #define URE_CHIP_VER_6010 0x0080
610 #define URE_CHIP_VER_7020 0x0100
611 #define URE_CHIP_VER_7030 0x0200
612 #define URE_CHIP_VER_7400 0x0400
613 #define URE_CHIP_VER_7410 0x0800