68 static int ure_debug = 0;
70 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
72 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
83 } while (0)
86 #define DEVPRINTF(...) do { } while (0)
87 #define DEVPRINTFN(...) do { } while (0)
99 	URE_DEV(ELECOM, EDCQUA3C, 0),
101 	URE_DEV(LENOVO, TBT3LANGEN2, 0),
102 	URE_DEV(LENOVO, ONELINK, 0),
105 	URE_DEV(LENOVO, USBCLAN, 0),
106 	URE_DEV(LENOVO, USBCLANGEN2, 0),
107 	URE_DEV(LENOVO, USBCLANHYBRID, 0),
108 	URE_DEV(MICROSOFT, WINDEVETH, 0),
279 	return (val & 0xff);  in ure_read_1()
296 	return (val & 0xffff);  in ure_read_2()
317 	val &= 0xff;  in ure_write_1()
338 	val &= 0xffff;  in ure_write_2()
364 	ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);  in ure_ocp_reg_read()
365 	reg = (addr & 0x0fff) | 0xb000;  in ure_ocp_reg_read()
375 	ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);  in ure_ocp_reg_write()
376 	reg = (addr & 0x0fff) | 0xb000;  in ure_ocp_reg_write()
422 		return (0);  in ure_miibus_writereg()
432 	return (0);  in ure_miibus_writereg()
451 	    (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)  in ure_miibus_statchg()
461 			sc->sc_rxstarted = 0;  in ure_miibus_statchg()
464 			if ((sc->sc_flags & URE_FLAG_8152) != 0)  in ure_miibus_statchg()
467 			sc->sc_rxstarted = 0;  in ure_miibus_statchg()
475 	if ((sc->sc_flags & URE_FLAG_LINK) == 0)  in ure_miibus_statchg()
528 	for (i = 0; i < URE_MAX_RX; i++) {  in ure_attach()
536 			.timeout = 0,	/* no timeout */  in ure_attach()
541 	if (error != 0) {  in ure_attach()
546 	for (i = 0; i < URE_MAX_TX; i++) {  in ure_attach()
559 	if (error != 0) {  in ure_attach()
572 	if (error != 0) {  in ure_attach()
576 	return (0);			/* success */  in ure_attach()
594 	return (0);  in ure_detach()
620 	for (mb = m; len > 0; mb = mb->m_next) {  in ure_makembuf()
650 		off = 0;  in ure_bulk_read_callback()
651 		pc = usbd_xfer_get_frame(xfer, 0);  in ure_bulk_read_callback()
654 		while (actlen > 0) {  in ure_bulk_read_callback()
716 				uether_rxmbuf(ue, m, 0);  in ure_bulk_read_callback()
727 		usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));  in ure_bulk_read_callback()
761 		if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);  in ure_bulk_write_callback()
766 		if ((sc->sc_flags & URE_FLAG_LINK) == 0) {  in ure_bulk_write_callback()
771 		pc = usbd_xfer_get_frame(xfer, 0);  in ure_bulk_write_callback()
774 		pos = 0;  in ure_bulk_write_callback()
828 			usbd_m_copy_in(pc, pos, m, 0, len);  in ure_bulk_write_callback()
845 		if (pos == 0)  in ure_bulk_write_callback()
849 		usbd_xfer_set_frame_len(xfer, 0, pos);  in ure_bulk_write_callback()
860 		if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);  in ure_bulk_write_callback()
883 	case 0x4c00:  in ure_read_chipver()
887 	case 0x4c10:  in ure_read_chipver()
891 	case 0x5c00:  in ure_read_chipver()
895 	case 0x5c10:  in ure_read_chipver()
899 	case 0x5c20:  in ure_read_chipver()
903 	case 0x5c30:  in ure_read_chipver()
907 	case 0x6000:  in ure_read_chipver()
911 	case 0x6010:  in ure_read_chipver()
915 	case 0x7020:  in ure_read_chipver()
919 	case 0x7030:  in ure_read_chipver()
923 	case 0x7400:  in ure_read_chipver()
927 	case 0x7410:  in ure_read_chipver()
933 		    "unknown version 0x%04x\n", ver);  in ure_read_chipver()
945 	sbuf_new_for_sysctl(&sb, NULL, 0, req);  in ure_sysctl_chipver()
960 	sc->sc_rxstarted = 0;  in ure_attach_post()
961 	sc->sc_phyno = 0;  in ure_attach_post()
984 		arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0);  in ure_attach_post()
985 		sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */  in ure_attach_post()
986 		sc->sc_ue.ue_eaddr[0] |= 0x02;  /* locally administered */  in ure_attach_post()
1012 	if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);  in ure_attach_post_sub()
1013 	if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0);  in ure_attach_post_sub()
1014 	if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0);  in ure_attach_post_sub()
1017 	if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0);  in ure_attach_post_sub()
1025 		ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);  in ure_attach_post_sub()
1028 		error = 0;  in ure_attach_post_sub()
1033 		    BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);  in ure_attach_post_sub()
1040 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,  in ure_attach_post_sub()
1057 	if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)  in ure_init()
1138 	usbd_xfer_set_stall(sc->sc_tx_xfer[0]);  in ure_init()
1141 	if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);  in ure_init()
1157 	for (int i = 0; i < URE_MAX_RX; i++)  in ure_tick()
1161 	for (int i = 0; i < URE_MAX_TX; i++)  in ure_tick()
1170 		if ((sc->sc_flags & URE_FLAG_LINK) == 0  in ure_tick()
1174 			sc->sc_rxstarted = 0;  in ure_tick()
1187 		hashes[0] |= (1 << h);  in ure_hash_maddr()
1202 	uint32_t h, hashes[2] = { 0, 0 };  in ure_rxfilter()
1214 		hashes[0] = hashes[1] = 0xffffffff;  in ure_rxfilter()
1221 	h = bswap32(hashes[0]);  in ure_rxfilter()
1222 	hashes[0] = bswap32(hashes[1]);  in ure_rxfilter()
1229 	ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);  in ure_rxfilter()
1244 		for (i = 0; i != URE_MAX_RX; i++)  in ure_start()
1248 	for (i = 0; i != URE_MAX_TX; i++)  in ure_start()
1259 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_reset()
1293 		reg = ure_ocp_reg_read(sc, 0xa5d4);  in ure_ifmedia_upd()
1296 		anar = gig = 0;  in ure_ifmedia_upd()
1332 		ure_ocp_reg_write(sc, 0xa5d4, reg);  in ure_ifmedia_upd()
1337 		return (0);  in ure_ifmedia_upd()
1397 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);  in ure_add_media_types()
1398 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);  in ure_add_media_types()
1399 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);  in ure_add_media_types()
1400 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);  in ure_add_media_types()
1401 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);  in ure_add_media_types()
1402 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL);  in ure_add_media_types()
1418 				URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);  in ure_link_state()
1420 				URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);  in ure_link_state()
1438 		return (0);  in ure_get_link_status()
1452 	error = 0;  in ure_ioctl()
1453 	reinit = 0;  in ure_ioctl()
1458 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&  in ure_ioctl()
1459 		    (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {  in ure_ioctl()
1463 		if ((mask & IFCAP_TXCSUM) != 0 &&  in ure_ioctl()
1464 		    (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {  in ure_ioctl()
1467 		if ((mask & IFCAP_RXCSUM) != 0 &&  in ure_ioctl()
1468 		    (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {  in ure_ioctl()
1471 		if ((mask & IFCAP_TXCSUM_IPV6) != 0 &&  in ure_ioctl()
1472 		    (if_getcapabilities(ifp) & IFCAP_TXCSUM_IPV6) != 0) {  in ure_ioctl()
1475 		if ((mask & IFCAP_RXCSUM_IPV6) != 0 &&  in ure_ioctl()
1476 		    (if_getcapabilities(ifp) & IFCAP_RXCSUM_IPV6) != 0) {  in ure_ioctl()
1479 		if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING)  in ure_ioctl()
1480 			if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);  in ure_ioctl()
1482 			reinit = 0;  in ure_ioctl()
1484 		if (reinit > 0)  in ure_ioctl()
1570 	memset(u1u2, 0x00, sizeof(u1u2));  in ure_rtl8153_init()
1574 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8153_init()
1584 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8153_init()
1610 		    0)  in ure_rtl8153_init()
1636 	ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);  in ure_rtl8153_init()
1642 	memset(u1u2, 0xff, sizeof(u1u2));  in ure_rtl8153_init()
1665 	memset(u1u2, 0x00, sizeof(u1u2));  in ure_rtl8153_init()
1690 	ure_sram_write(sc, URE_SRAM_IMPEDANCE, 0x0b13);  in ure_rtl8153_init()
1694 	ure_sram_write(sc, URE_SRAM_LPF_CFG, 0xf70f);  in ure_rtl8153_init()
1697 	ure_sram_write(sc, URE_SRAM_10M_AMP1, 0x00af);  in ure_rtl8153_init()
1698 	ure_sram_write(sc, URE_SRAM_10M_AMP2, 0x0208);  in ure_rtl8153_init()
1712 	memset(u1u2, 0xff, sizeof(u1u2));  in ure_rtl8153_init()
1724 		URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01);  in ure_rtl8153b_init()
1725 		ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0);  in ure_rtl8153b_init()
1726 		URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020);  in ure_rtl8153b_init()
1730 		URE_SETBIT_2(sc, 0xb460, URE_MCU_TYPE_USB, 0x08);  in ure_rtl8153b_init()
1740 		if ((ure_read_2(sc, 0xd3ae, URE_MCU_TYPE_PLA) & 0x0002) &&  in ure_rtl8153b_init()
1741 		    !(ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0020)) {  in ure_rtl8153b_init()
1742 			for (i=0; i < 100; i++) {  in ure_rtl8153b_init()
1743 				if (ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0004)  in ure_rtl8153b_init()
1750 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8153b_init()
1760 	val = ure_phy_status(sc, 0);  in ure_rtl8153b_init()
1763 		ure_ocp_reg_write(sc, 0xa468,  in ure_rtl8153b_init()
1764 		    ure_ocp_reg_read(sc, 0xa468) & ~0x0a);  in ure_rtl8153b_init()
1766 			ure_ocp_reg_write(sc, 0xa466,  in ure_rtl8153b_init()
1767 				ure_ocp_reg_read(sc, 0xa466) & ~0x01);  in ure_rtl8153b_init()
1782 	ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff);  in ure_rtl8153b_init()
1793 	URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01);  in ure_rtl8153b_init()
1810 		URE_CLRBIT_2(sc, 0xc010, URE_MCU_TYPE_PLA, 0x0800);  in ure_rtl8153b_init()
1811 		URE_SETBIT_2(sc, 0xe854, URE_MCU_TYPE_PLA, 0x0001);  in ure_rtl8153b_init()
1816 		if (!(ure_read_1(sc, 0xdc6b, URE_MCU_TYPE_PLA) & 0x80)) {  in ure_rtl8153b_init()
1818 			val |= URE_FLOW_CTRL_PATCH_OPT | 0x0100;  in ure_rtl8153b_init()
1819 			val &= ~0x08;  in ure_rtl8153b_init()
1836 		ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403);  in ure_rtl8153b_init()
1838 		val &= ~0xff;  in ure_rtl8153b_init()
1839 		val |= URE_MAC_CLK_SPDWN_EN | 0x03;  in ure_rtl8153b_init()
1850 		URE_SETBIT_1(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x02);  in ure_rtl8153b_init()
1889 		for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8153b_nic_reset()
1900 		for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8153b_nic_reset()
1912 	val = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA);  in ure_rtl8153b_nic_reset()
1913 	val &= ~0x00c0;  in ure_rtl8153b_nic_reset()
1915 		val |= 0x00c0;  in ure_rtl8153b_nic_reset()
1916 	ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, val);  in ure_rtl8153b_nic_reset()
1929 		ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0400);  in ure_rtl8153b_nic_reset()
1930 		ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0800);  in ure_rtl8153b_nic_reset()
1932 		ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0200);  in ure_rtl8153b_nic_reset()
1933 		ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0400);  in ure_rtl8153b_nic_reset()
1943 		ure_write_2(sc, 0xc0a2, URE_MCU_TYPE_PLA,  in ure_rtl8153b_nic_reset()
1944 		    (ure_read_2(sc, 0xc0a2, URE_MCU_TYPE_PLA) & ~0xfff) | 0x08);  in ure_rtl8153b_nic_reset()
1945 		ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 0x00600400);  in ure_rtl8153b_nic_reset()
1953 		URE_SETBIT_2(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x0002);  in ure_rtl8153b_nic_reset()
1955 		ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 0x0008);  in ure_rtl8153b_nic_reset()
1956 		ure_write_2(sc, 0xe61a, URE_MCU_TYPE_PLA,  in ure_rtl8153b_nic_reset()
1957 		    (URE_FRAMELEN(val) + 0x100) / 16 );  in ure_rtl8153b_nic_reset()
1963 		URE_CLRBIT_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0x300);  in ure_rtl8153b_nic_reset()
1985 	if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));  in ure_stop()
1987 	sc->sc_rxstarted = 0;  in ure_stop()
1992 	for (int i = 0; i < URE_MAX_RX; i++)  in ure_stop()
1994 	for (int i = 0; i < URE_MAX_TX; i++)  in ure_stop()
2003 		ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff);  in ure_disable_teredo()
2009 	ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);  in ure_disable_teredo()
2010 	ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);  in ure_disable_teredo()
2024 		for (i = 0; i < 20; i++) {  in ure_enable_aldps()
2026 			if (ure_ocp_reg_read(sc, 0xe000) & 0x0100)  in ure_enable_aldps()
2038 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_phy_status()
2074 	ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);  in ure_rtl8152_nic_reset()
2079 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8152_nic_reset()
2089 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8152_nic_reset()
2131 	m->m_pkthdr.csum_flags = 0;  in ure_rxcsum()
2139 	tcp = udp = 0;  in ure_rxcsum()
2141 	flags = 0;  in ure_rxcsum()
2145 		flags = 0;  in ure_rxcsum()
2158 		m->m_pkthdr.csum_data = 0xFFFF;  in ure_rxcsum()
2165  * If the L4 checksum offset is larger than 0x7ff (2047), return failure.
2170  * Returns 0 for success, and 1 if the packet cannot be checksummed and
2184 	*regout = 0;  in ure_txcsum()
2186 	if (flags == 0)  in ure_txcsum()
2187 		return (0);  in ure_txcsum()
2206 		return (0);  in ure_txcsum()
2209 	reg = 0;  in ure_txcsum()
2243 	return 0;  in ure_txcsum()