68 static int ure_debug = 0;
70 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
72 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
83 } while (0)
86 #define DEVPRINTF(...) do { } while (0)
87 #define DEVPRINTFN(...) do { } while (0)
100 	URE_DEV(LENOVO, TBT3LANGEN2, 0),
101 	URE_DEV(LENOVO, ONELINK, 0),
104 	URE_DEV(LENOVO, USBCLAN, 0),
105 	URE_DEV(LENOVO, USBCLANGEN2, 0),
106 	URE_DEV(LENOVO, USBCLANHYBRID, 0),
107 	URE_DEV(MICROSOFT, WINDEVETH, 0),
278 	return (val & 0xff);  in ure_read_1()
295 	return (val & 0xffff);  in ure_read_2()
316 	val &= 0xff;  in ure_write_1()
337 	val &= 0xffff;  in ure_write_2()
363 	ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);  in ure_ocp_reg_read()
364 	reg = (addr & 0x0fff) | 0xb000;  in ure_ocp_reg_read()
374 	ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);  in ure_ocp_reg_write()
375 	reg = (addr & 0x0fff) | 0xb000;  in ure_ocp_reg_write()
421 		return (0);  in ure_miibus_writereg()
431 	return (0);  in ure_miibus_writereg()
450 	    (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)  in ure_miibus_statchg()
460 			sc->sc_rxstarted = 0;  in ure_miibus_statchg()
463 			if ((sc->sc_flags & URE_FLAG_8152) != 0)  in ure_miibus_statchg()
466 			sc->sc_rxstarted = 0;  in ure_miibus_statchg()
474 	if ((sc->sc_flags & URE_FLAG_LINK) == 0)  in ure_miibus_statchg()
527 	for (i = 0; i < URE_MAX_RX; i++) {  in ure_attach()
535 			.timeout = 0,	/* no timeout */  in ure_attach()
540 	if (error != 0) {  in ure_attach()
545 	for (i = 0; i < URE_MAX_TX; i++) {  in ure_attach()
558 	if (error != 0) {  in ure_attach()
571 	if (error != 0) {  in ure_attach()
575 	return (0);			/* success */  in ure_attach()
593 	return (0);  in ure_detach()
619 	for (mb = m; len > 0; mb = mb->m_next) {  in ure_makembuf()
649 		off = 0;  in ure_bulk_read_callback()
650 		pc = usbd_xfer_get_frame(xfer, 0);  in ure_bulk_read_callback()
653 		while (actlen > 0) {  in ure_bulk_read_callback()
720 		usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));  in ure_bulk_read_callback()
754 		if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);  in ure_bulk_write_callback()
759 		if ((sc->sc_flags & URE_FLAG_LINK) == 0) {  in ure_bulk_write_callback()
764 		pc = usbd_xfer_get_frame(xfer, 0);  in ure_bulk_write_callback()
767 		pos = 0;  in ure_bulk_write_callback()
821 			usbd_m_copy_in(pc, pos, m, 0, len);  in ure_bulk_write_callback()
838 		if (pos == 0)  in ure_bulk_write_callback()
842 		usbd_xfer_set_frame_len(xfer, 0, pos);  in ure_bulk_write_callback()
853 		if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);  in ure_bulk_write_callback()
876 	case 0x4c00:  in ure_read_chipver()
880 	case 0x4c10:  in ure_read_chipver()
884 	case 0x5c00:  in ure_read_chipver()
888 	case 0x5c10:  in ure_read_chipver()
892 	case 0x5c20:  in ure_read_chipver()
896 	case 0x5c30:  in ure_read_chipver()
900 	case 0x6000:  in ure_read_chipver()
904 	case 0x6010:  in ure_read_chipver()
908 	case 0x7020:  in ure_read_chipver()
912 	case 0x7030:  in ure_read_chipver()
916 	case 0x7400:  in ure_read_chipver()
920 	case 0x7410:  in ure_read_chipver()
926 		    "unknown version 0x%04x\n", ver);  in ure_read_chipver()
938 	sbuf_new_for_sysctl(&sb, NULL, 0, req);  in ure_sysctl_chipver()
953 	sc->sc_rxstarted = 0;  in ure_attach_post()
954 	sc->sc_phyno = 0;  in ure_attach_post()
977 		arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0);  in ure_attach_post()
978 		sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */  in ure_attach_post()
979 		sc->sc_ue.ue_eaddr[0] |= 0x02;  /* locally administered */  in ure_attach_post()
1005 	if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);  in ure_attach_post_sub()
1006 	if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0);  in ure_attach_post_sub()
1007 	if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0);  in ure_attach_post_sub()
1010 	if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0);  in ure_attach_post_sub()
1018 		ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);  in ure_attach_post_sub()
1021 		error = 0;  in ure_attach_post_sub()
1026 		    BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);  in ure_attach_post_sub()
1033 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,  in ure_attach_post_sub()
1050 	if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)  in ure_init()
1131 	usbd_xfer_set_stall(sc->sc_tx_xfer[0]);  in ure_init()
1134 	if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);  in ure_init()
1150 	for (int i = 0; i < URE_MAX_RX; i++)  in ure_tick()
1154 	for (int i = 0; i < URE_MAX_TX; i++)  in ure_tick()
1163 		if ((sc->sc_flags & URE_FLAG_LINK) == 0  in ure_tick()
1167 			sc->sc_rxstarted = 0;  in ure_tick()
1180 		hashes[0] |= (1 << h);  in ure_hash_maddr()
1195 	uint32_t h, hashes[2] = { 0, 0 };  in ure_rxfilter()
1207 		hashes[0] = hashes[1] = 0xffffffff;  in ure_rxfilter()
1214 	h = bswap32(hashes[0]);  in ure_rxfilter()
1215 	hashes[0] = bswap32(hashes[1]);  in ure_rxfilter()
1222 	ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);  in ure_rxfilter()
1237 		for (i = 0; i != URE_MAX_RX; i++)  in ure_start()
1241 	for (i = 0; i != URE_MAX_TX; i++)  in ure_start()
1252 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_reset()
1286 		reg = ure_ocp_reg_read(sc, 0xa5d4);  in ure_ifmedia_upd()
1289 		anar = gig = 0;  in ure_ifmedia_upd()
1325 		ure_ocp_reg_write(sc, 0xa5d4, reg);  in ure_ifmedia_upd()
1330 		return (0);  in ure_ifmedia_upd()
1390 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);  in ure_add_media_types()
1391 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);  in ure_add_media_types()
1392 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);  in ure_add_media_types()
1393 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);  in ure_add_media_types()
1394 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);  in ure_add_media_types()
1395 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL);  in ure_add_media_types()
1411 				URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);  in ure_link_state()
1413 				URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);  in ure_link_state()
1431 		return (0);  in ure_get_link_status()
1445 	error = 0;  in ure_ioctl()
1446 	reinit = 0;  in ure_ioctl()
1451 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&  in ure_ioctl()
1452 		    (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {  in ure_ioctl()
1456 		if ((mask & IFCAP_TXCSUM) != 0 &&  in ure_ioctl()
1457 		    (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {  in ure_ioctl()
1460 		if ((mask & IFCAP_RXCSUM) != 0 &&  in ure_ioctl()
1461 		    (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {  in ure_ioctl()
1464 		if ((mask & IFCAP_TXCSUM_IPV6) != 0 &&  in ure_ioctl()
1465 		    (if_getcapabilities(ifp) & IFCAP_TXCSUM_IPV6) != 0) {  in ure_ioctl()
1468 		if ((mask & IFCAP_RXCSUM_IPV6) != 0 &&  in ure_ioctl()
1469 		    (if_getcapabilities(ifp) & IFCAP_RXCSUM_IPV6) != 0) {  in ure_ioctl()
1472 		if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING)  in ure_ioctl()
1473 			if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);  in ure_ioctl()
1475 			reinit = 0;  in ure_ioctl()
1477 		if (reinit > 0)  in ure_ioctl()
1563 	memset(u1u2, 0x00, sizeof(u1u2));  in ure_rtl8153_init()
1567 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8153_init()
1577 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8153_init()
1603 		    0)  in ure_rtl8153_init()
1629 	ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);  in ure_rtl8153_init()
1635 	memset(u1u2, 0xff, sizeof(u1u2));  in ure_rtl8153_init()
1658 	memset(u1u2, 0x00, sizeof(u1u2));  in ure_rtl8153_init()
1683 	ure_sram_write(sc, URE_SRAM_IMPEDANCE, 0x0b13);  in ure_rtl8153_init()
1687 	ure_sram_write(sc, URE_SRAM_LPF_CFG, 0xf70f);  in ure_rtl8153_init()
1690 	ure_sram_write(sc, URE_SRAM_10M_AMP1, 0x00af);  in ure_rtl8153_init()
1691 	ure_sram_write(sc, URE_SRAM_10M_AMP2, 0x0208);  in ure_rtl8153_init()
1705 	memset(u1u2, 0xff, sizeof(u1u2));  in ure_rtl8153_init()
1717 		URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01);  in ure_rtl8153b_init()
1718 		ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0);  in ure_rtl8153b_init()
1719 		URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020);  in ure_rtl8153b_init()
1723 		URE_SETBIT_2(sc, 0xb460, URE_MCU_TYPE_USB, 0x08);  in ure_rtl8153b_init()
1733 		if ((ure_read_2(sc, 0xd3ae, URE_MCU_TYPE_PLA) & 0x0002) &&  in ure_rtl8153b_init()
1734 		    !(ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0020)) {  in ure_rtl8153b_init()
1735 			for (i=0; i < 100; i++) {  in ure_rtl8153b_init()
1736 				if (ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0004)  in ure_rtl8153b_init()
1743 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8153b_init()
1753 	val = ure_phy_status(sc, 0);  in ure_rtl8153b_init()
1756 		ure_ocp_reg_write(sc, 0xa468,  in ure_rtl8153b_init()
1757 		    ure_ocp_reg_read(sc, 0xa468) & ~0x0a);  in ure_rtl8153b_init()
1759 			ure_ocp_reg_write(sc, 0xa466,  in ure_rtl8153b_init()
1760 				ure_ocp_reg_read(sc, 0xa466) & ~0x01);  in ure_rtl8153b_init()
1775 	ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff);  in ure_rtl8153b_init()
1786 	URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01);  in ure_rtl8153b_init()
1803 		URE_CLRBIT_2(sc, 0xc010, URE_MCU_TYPE_PLA, 0x0800);  in ure_rtl8153b_init()
1804 		URE_SETBIT_2(sc, 0xe854, URE_MCU_TYPE_PLA, 0x0001);  in ure_rtl8153b_init()
1809 		if (!(ure_read_1(sc, 0xdc6b, URE_MCU_TYPE_PLA) & 0x80)) {  in ure_rtl8153b_init()
1811 			val |= URE_FLOW_CTRL_PATCH_OPT | 0x0100;  in ure_rtl8153b_init()
1812 			val &= ~0x08;  in ure_rtl8153b_init()
1829 		ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403);  in ure_rtl8153b_init()
1831 		val &= ~0xff;  in ure_rtl8153b_init()
1832 		val |= URE_MAC_CLK_SPDWN_EN | 0x03;  in ure_rtl8153b_init()
1843 		URE_SETBIT_1(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x02);  in ure_rtl8153b_init()
1882 		for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8153b_nic_reset()
1893 		for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8153b_nic_reset()
1905 	val = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA);  in ure_rtl8153b_nic_reset()
1906 	val &= ~0x00c0;  in ure_rtl8153b_nic_reset()
1908 		val |= 0x00c0;  in ure_rtl8153b_nic_reset()
1909 	ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, val);  in ure_rtl8153b_nic_reset()
1922 		ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0400);  in ure_rtl8153b_nic_reset()
1923 		ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0800);  in ure_rtl8153b_nic_reset()
1925 		ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0200);  in ure_rtl8153b_nic_reset()
1926 		ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0400);  in ure_rtl8153b_nic_reset()
1936 		ure_write_2(sc, 0xc0a2, URE_MCU_TYPE_PLA,  in ure_rtl8153b_nic_reset()
1937 		    (ure_read_2(sc, 0xc0a2, URE_MCU_TYPE_PLA) & ~0xfff) | 0x08);  in ure_rtl8153b_nic_reset()
1938 		ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 0x00600400);  in ure_rtl8153b_nic_reset()
1946 		URE_SETBIT_2(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x0002);  in ure_rtl8153b_nic_reset()
1948 		ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 0x0008);  in ure_rtl8153b_nic_reset()
1949 		ure_write_2(sc, 0xe61a, URE_MCU_TYPE_PLA,  in ure_rtl8153b_nic_reset()
1950 		    (URE_FRAMELEN(val) + 0x100) / 16 );  in ure_rtl8153b_nic_reset()
1956 		URE_CLRBIT_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0x300);  in ure_rtl8153b_nic_reset()
1978 	if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));  in ure_stop()
1980 	sc->sc_rxstarted = 0;  in ure_stop()
1985 	for (int i = 0; i < URE_MAX_RX; i++)  in ure_stop()
1987 	for (int i = 0; i < URE_MAX_TX; i++)  in ure_stop()
1996 		ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff);  in ure_disable_teredo()
2002 	ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);  in ure_disable_teredo()
2003 	ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);  in ure_disable_teredo()
2017 		for (i = 0; i < 20; i++) {  in ure_enable_aldps()
2019 			if (ure_ocp_reg_read(sc, 0xe000) & 0x0100)  in ure_enable_aldps()
2031 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_phy_status()
2067 	ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);  in ure_rtl8152_nic_reset()
2072 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8152_nic_reset()
2082 	for (i = 0; i < URE_TIMEOUT; i++) {  in ure_rtl8152_nic_reset()
2124 	m->m_pkthdr.csum_flags = 0;  in ure_rxcsum()
2132 	tcp = udp = 0;  in ure_rxcsum()
2134 	flags = 0;  in ure_rxcsum()
2138 		flags = 0;  in ure_rxcsum()
2151 		m->m_pkthdr.csum_data = 0xFFFF;  in ure_rxcsum()
2158  * If the L4 checksum offset is larger than 0x7ff (2047), return failure.
2163  * Returns 0 for success, and 1 if the packet cannot be checksummed and
2177 	*regout = 0;  in ure_txcsum()
2179 	if (flags == 0)  in ure_txcsum()
2180 		return (0);  in ure_txcsum()
2199 		return (0);  in ure_txcsum()
2202 	reg = 0;  in ure_txcsum()
2236 	return 0;  in ure_txcsum()