Lines Matching +full:0 +full:x0c8
40 #define UVR_WRITE_REG 0xA0
41 #define UVR_READ_REG 0xA1
42 #define UVR_GET_STATS 0xA2
45 #define ETH_ID_REV 0x000
46 #define ETH_ID_REV_CHIP_ID_MASK_ 0xFFFF0000UL
47 #define ETH_ID_REV_CHIP_REV_MASK_ 0x0000FFFFUL
48 #define ETH_ID_REV_CHIP_ID_7800_ 0x7800
49 #define ETH_ID_REV_CHIP_ID_7801_ 0x7801
50 #define ETH_ID_REV_CHIP_ID_7850_ 0x7850
53 #define ETH_INT_STS 0x00C
54 #define ETH_INT_STS_CLEAR_ALL_ 0xFFFFFFFFUL
57 #define ETH_HW_CFG 0x010
58 #define ETH_HW_CFG_LED3_EN_ (0x1UL << 23)
59 #define ETH_HW_CFG_LED2_EN_ (0x1UL << 22)
60 #define ETH_HW_CFG_LED1_EN_ (0x1UL << 21)
61 #define ETH_HW_CFG_LEDO_EN_ (0x1UL << 20)
62 #define ETH_HW_CFG_MEF_ (0x1UL << 4)
63 #define ETH_HW_CFG_ETC_ (0x1UL << 3)
64 #define ETH_HW_CFG_LRST_ (0x1UL << 1) /* Lite reset */
65 #define ETH_HW_CFG_SRST_ (0x1UL << 0) /* Soft reset */
68 #define ETH_PMT_CTL 0x014
69 #define ETH_PMT_CTL_PHY_RST_ (0x1UL << 4) /* PHY reset */
70 #define ETH_PMT_CTL_WOL_EN_ (0x1UL << 3) /* PHY wake-on-lan */
71 #define ETH_PMT_CTL_PHY_WAKE_EN_ (0x1UL << 2) /* PHY int wake */
73 /* GPIO Configuration 0 Register. */
74 #define ETH_GPIO_CFG0 0x018
77 #define ETH_GPIO_CFG1 0x01C
80 #define ETH_GPIO_WAKE 0x020
83 #define RX_CMD_A_RED_ (0x1UL << 22) /* Receive Error Det */
84 #define RX_CMD_A_ICSM_ (0x1UL << 14)
85 #define RX_CMD_A_LEN_MASK_ 0x00003FFFUL
88 #define TX_CMD_A_LEN_MASK_ 0x000FFFFFUL
89 #define TX_CMD_A_FCS_ (0x1UL << 22)
92 #define ETH_DP_SEL 0x024
93 #define ETH_DP_SEL_DPRDY_ (0x1UL << 31)
94 #define ETH_DP_SEL_RSEL_VLAN_DA_ (0x1UL << 0) /* RFE VLAN/DA Hash */
95 #define ETH_DP_SEL_RSEL_MASK_ 0x0000000F
100 #define ETH_DP_CMD 0x028
101 #define ETH_DP_CMD_WRITE_ (0x1UL << 0) /* 1 for write */
102 #define ETH_DP_CMD_READ_ (0x0UL << 0) /* 0 for read */
105 #define ETH_DP_ADDR 0x02C
108 #define ETH_DP_DATA 0x030
111 #define ETH_E2P_CMD 0x040
112 #define ETH_E2P_CMD_MASK_ 0x70000000UL
113 #define ETH_E2P_CMD_ADDR_MASK_ 0x000001FFUL
114 #define ETH_E2P_CMD_BUSY_ (0x1UL << 31)
115 #define ETH_E2P_CMD_READ_ (0x0UL << 28)
116 #define ETH_E2P_CMD_WRITE_ (0x3UL << 28)
117 #define ETH_E2P_CMD_ERASE_ (0x5UL << 28)
118 #define ETH_E2P_CMD_RELOAD_ (0x7UL << 28)
119 #define ETH_E2P_CMD_TIMEOUT_ (0x1UL << 10)
120 #define ETH_E2P_MAC_OFFSET 0x01
121 #define ETH_E2P_INDICATOR_OFFSET 0x00
124 #define ETH_E2P_DATA 0x044
125 #define ETH_E2P_INDICATOR 0xA5 /* EEPROM is present */
133 #define ETH_RFE_CTL 0x0B0
134 #define ETH_RFE_CTL_IGMP_COE_ (0x1U << 14)
135 #define ETH_RFE_CTL_ICMP_COE_ (0x1U << 13)
136 #define ETH_RFE_CTL_TCPUDP_COE_ (0x1U << 12)
137 #define ETH_RFE_CTL_IP_COE_ (0x1U << 11)
138 #define ETH_RFE_CTL_BCAST_EN_ (0x1U << 10)
139 #define ETH_RFE_CTL_MCAST_EN_ (0x1U << 9)
140 #define ETH_RFE_CTL_UCAST_EN_ (0x1U << 8)
141 #define ETH_RFE_CTL_VLAN_FILTER_ (0x1U << 5)
142 #define ETH_RFE_CTL_MCAST_HASH_ (0x1U << 3)
143 #define ETH_RFE_CTL_DA_PERFECT_ (0x1U << 1)
146 #define ETH_FCT_RX_FIFO_END 0x0C8
147 #define ETH_FCT_RX_FIFO_END_MASK_ 0x0000007FUL
151 #define ETH_FCT_TX_FIFO_END 0x0CC
152 #define ETH_FCT_TX_FIFO_END_MASK_ 0x0000003FUL
155 /* USB Configuration Register 0 */
156 #define ETH_USB_CFG0 0x080
157 #define ETH_USB_CFG_BIR_ (0x1U << 6) /* Bulk-In Empty resp */
158 #define ETH_USB_CFG_BCE_ (0x1U << 5) /* Burst Cap Enable */
161 #define ETH_USB_CFG1 0x084
164 #define ETH_USB_CFG2 0x088
167 #define MUGE_CONFIG_INDEX 0
170 #define ETH_BURST_CAP 0x090
174 #define ETH_BULK_IN_DLY 0x094
175 #define MUGE_DEFAULT_BULK_IN_DELAY 0x0800
178 #define ETH_INT_EP_CTL 0x098
179 #define ETH_INT_ENP_PHY_INT (0x1U << 17) /* PHY Enable */
184 #define MUGE_PHY_INTR_LINK_CHANGE (0x1U << 13)
185 #define MUGE_PHY_INTR_ANEG_COMP (0x1U << 10)
186 #define MUGE_EXT_PAGE_ACCESS 0x1F
187 #define MUGE_EXT_PAGE_SPACE_0 0x0000
188 #define MUGE_EXT_PAGE_SPACE_1 0x0001
189 #define MUGE_EXT_PAGE_SPACE_2 0x0002
194 #define MUGE_EXT_MODE_CTRL 0x0013
195 #define MUGE_EXT_MODE_CTRL_MDIX_MASK_ 0x000C
196 #define MUGE_EXT_MODE_CTRL_AUTO_MDIX_ 0x0000
199 #define ETH_FCT_FLOW 0x0D0
202 #define ETH_FCT_RX_CTL 0x0C0
205 #define ETH_FCT_TX_CTL 0x0C4
206 #define ETH_FCT_TX_CTL_EN_ (0x1U << 31)
209 #define ETH_MAC_CR 0x100
210 #define ETH_MAC_CR_GMII_EN_ (0x1U << 19) /* GMII Enable */
211 #define ETH_MAC_CR_AUTO_DUPLEX_ (0x1U << 12)
212 #define ETH_MAC_CR_AUTO_SPEED_ (0x1U << 11)
215 #define ETH_MAC_RX 0x104
216 #define ETH_MAC_RX_MAX_FR_SIZE_MASK_ 0x3FFF0000
218 #define ETH_MAC_RX_EN_ (0x1U << 0) /* Enable Receiver */
221 #define ETH_MAC_TX 0x108
222 #define ETH_MAC_TX_TXEN_ (0x1U << 0) /* Enable Transmitter */
225 #define ETH_FLOW 0x10C
226 #define ETH_FLOW_CR_TX_FCEN_ (0x1U << 30) /* TX FC Enable */
227 #define ETH_FLOW_CR_RX_FCEN_ (0x1U << 29) /* RX FC Enable */
230 #define ETH_RX_ADDRH 0x118 /* High */
231 #define ETH_RX_ADDRL 0x11C /* Low */
234 #define ETH_MII_ACC 0x120
235 #define ETH_MII_ACC_MII_BUSY_ (0x1UL << 0)
236 #define ETH_MII_ACC_MII_READ_ (0x0UL << 1)
237 #define ETH_MII_ACC_MII_WRITE_ (0x1UL << 1)
240 #define ETH_MII_DATA 0x124
243 #define ETH_MAF_BASE 0x400
244 #define ETH_MAF_HIx 0x00
245 #define ETH_MAF_LOx 0x04
247 #define ETH_MAF_HI_VALID_ (0x1UL << 31)
248 #define ETH_MAF_HI_TYPE_SRC_ (0x1UL << 30)
249 #define ETH_MAF_HI_TYPE_DST_ (0x0UL << 30)
257 #define OTP_BASE_ADDR 0x01000
258 #define OTP_PWR_DN (OTP_BASE_ADDR + 4 * 0x00)
259 #define OTP_PWR_DN_PWRDN_N 0x01
260 #define OTP_ADDR1 (OTP_BASE_ADDR + 4 * 0x01)
261 #define OTP_ADDR1_15_11 0x1F
262 #define OTP_ADDR2 (OTP_BASE_ADDR + 4 * 0x02)
263 #define OTP_ADDR2_10_3 0xFF
264 #define OTP_ADDR3 (OTP_BASE_ADDR + 4 * 0x03)
265 #define OTP_ADDR3_2_0 0x03
266 #define OTP_RD_DATA (OTP_BASE_ADDR + 4 * 0x06)
267 #define OTP_FUNC_CMD (OTP_BASE_ADDR + 4 * 0x08)
268 #define OTP_FUNC_CMD_RESET 0x04
269 #define OTP_FUNC_CMD_PROGRAM_ 0x02
270 #define OTP_FUNC_CMD_READ_ 0x01
271 #define OTP_MAC_OFFSET 0x01
272 #define OTP_INDICATOR_OFFSET 0x00
273 #define OTP_INDICATOR_1 0xF3
274 #define OTP_INDICATOR_2 0xF7
275 #define OTP_CMD_GO (OTP_BASE_ADDR + 4 * 0x0A)
276 #define OTP_CMD_GO_GO_ 0x01
277 #define OTP_STATUS (OTP_BASE_ADDR + 4 * 0x0A)
278 #define OTP_STATUS_OTP_LOCK_ 0x10
279 #define OTP_STATUS_BUSY_ 0x01
282 #if 0
283 #define ETH_BOS_ATTR 0x050
284 #define ETH_SS_ATTR 0x054
285 #define ETH_HS_ATTR 0x058
286 #define ETH_FS_ATTR 0x05C
287 #define ETH_STRNG_ATTR0 0x060
288 #define ETH_STRNG_ATTR1 0x064
289 #define ETH_STRNGFLAG_ATTR 0x068
290 #define ETH_SW_GP_0 0x06C
291 #define ETH_SW_GP_1 0x070
292 #define ETH_SW_GP_2 0x074
293 #define ETH_VLAN_TYPE 0x0B4
294 #define ETH_RX_DP_STOR 0x0D4
295 #define ETH_TX_DP_STOR 0x0D8
296 #define ETH_LTM_BELT_IDLE0 0x0E0
297 #define ETH_LTM_BELT_IDLE1 0x0E4
298 #define ETH_LTM_BELT_ACT0 0x0E8
299 #define ETH_LTM_BELT_ACT1 0x0EC
300 #define ETH_LTM_INACTIVE0 0x0F0
301 #define ETH_LTM_INACTIVE1 0x0F4
303 #define ETH_RAND_SEED 0x110
304 #define ETH_ERR_STS 0x114
306 #define ETH_EEE_TX_LPI_REQ_DLY 0x130
307 #define ETH_EEE_TW_TX_SYS 0x134
308 #define ETH_EEE_TX_LPI_REM_DLY 0x138
310 #define ETH_WUCSR1 0x140
311 #define ETH_WK_SRC 0x144
312 #define ETH_WUF_CFGx 0x150
313 #define ETH_WUF_MASKx 0x200
314 #define ETH_WUCSR2 0x600
316 #define ETH_NS1_IPV6_ADDR_DEST0 0x610
317 #define ETH_NS1_IPV6_ADDR_DEST1 0x614
318 #define ETH_NS1_IPV6_ADDR_DEST2 0x618
319 #define ETH_NS1_IPV6_ADDR_DEST3 0x61C
321 #define ETH_NS1_IPV6_ADDR_SRC0 0x620
322 #define ETH_NS1_IPV6_ADDR_SRC1 0x624
323 #define ETH_NS1_IPV6_ADDR_SRC2 0x628
324 #define ETH_NS1_IPV6_ADDR_SRC3 0x62C
326 #define ETH_NS1_ICMPV6_ADDR0_0 0x630
327 #define ETH_NS1_ICMPV6_ADDR0_1 0x634
328 #define ETH_NS1_ICMPV6_ADDR0_2 0x638
329 #define ETH_NS1_ICMPV6_ADDR0_3 0x63C
331 #define ETH_NS1_ICMPV6_ADDR1_0 0x640
332 #define ETH_NS1_ICMPV6_ADDR1_1 0x644
333 #define ETH_NS1_ICMPV6_ADDR1_2 0x648
334 #define ETH_NS1_ICMPV6_ADDR1_3 0x64C
336 #define ETH_NS2_IPV6_ADDR_DEST0 0x650
337 #define ETH_NS2_IPV6_ADDR_DEST1 0x654
338 #define ETH_NS2_IPV6_ADDR_DEST2 0x658
339 #define ETH_NS2_IPV6_ADDR_DEST3 0x65C
341 #define ETH_NS2_IPV6_ADDR_SRC0 0x660
342 #define ETH_NS2_IPV6_ADDR_SRC1 0x664
343 #define ETH_NS2_IPV6_ADDR_SRC2 0x668
344 #define ETH_NS2_IPV6_ADDR_SRC3 0x66C
346 #define ETH_NS2_ICMPV6_ADDR0_0 0x670
347 #define ETH_NS2_ICMPV6_ADDR0_1 0x674
348 #define ETH_NS2_ICMPV6_ADDR0_2 0x678
349 #define ETH_NS2_ICMPV6_ADDR0_3 0x67C
351 #define ETH_NS2_ICMPV6_ADDR1_0 0x680
352 #define ETH_NS2_ICMPV6_ADDR1_1 0x684
353 #define ETH_NS2_ICMPV6_ADDR1_2 0x688
354 #define ETH_NS2_ICMPV6_ADDR1_3 0x68C
356 #define ETH_SYN_IPV4_ADDR_SRC 0x690
357 #define ETH_SYN_IPV4_ADDR_DEST 0x694
358 #define ETH_SYN_IPV4_TCP_PORTS 0x698
360 #define ETH_SYN_IPV6_ADDR_SRC0 0x69C
361 #define ETH_SYN_IPV6_ADDR_SRC1 0x6A0
362 #define ETH_SYN_IPV6_ADDR_SRC2 0x6A4
363 #define ETH_SYN_IPV6_ADDR_SRC3 0x6A8
365 #define ETH_SYN_IPV6_ADDR_DEST0 0x6AC
366 #define ETH_SYN_IPV6_ADDR_DEST1 0x6B0
367 #define ETH_SYN_IPV6_ADDR_DEST2 0x6B4
368 #define ETH_SYN_IPV6_ADDR_DEST3 0x6B8
370 #define ETH_SYN_IPV6_TCP_PORTS 0x6BC
371 #define ETH_ARP_SPA 0x6C0
372 #define ETH_ARP_TPA 0x6C4
373 #define ETH_PHY_DEV_ID 0x700