50 #define	XHCI_HCS1_DEVSLOT_MAX(x)((x) & 0xFF)  argument
51 #define	XHCI_HCS1_IRQ_MAX(x)	(((x) >> 8) & 0x3FF)  argument
52 #define	XHCI_HCS1_N_PORTS(x)	(((x) >> 24) & 0xFF)  argument
54 #define	XHCI_HCS2_IST(x)	((x) & 0xF)  argument
55 #define	XHCI_HCS2_ERST_MAX(x)	(((x) >> 4) & 0xF)  argument
56 #define	XHCI_HCS2_SPR(x)	(((x) >> 26) & 0x1)  argument
57 #define	XHCI_HCS2_SPB_MAX(x)	((((x) >> 16) & 0x3E0) | (((x) >> 27) & 0x1F))  argument
59 #define	XHCI_HCS3_U1_DEL(x)	((x) & 0xFF)  argument
60 #define	XHCI_HCS3_U2_DEL(x)	(((x) >> 16) & 0xFFFF)  argument
62 #define	XHCI_HCS0_AC64(x)	((x) & 0x1)		/* 64-bit capable */  argument
63 #define	XHCI_HCS0_BNC(x)	(((x) >> 1) & 0x1)	/* BW negotiation */  argument
64 #define	XHCI_HCS0_CSZ(x)	(((x) >> 2) & 0x1)	/* context size */  argument
65 #define	XHCI_HCS0_PPC(x)	(((x) >> 3) & 0x1)	/* port power control */  argument
66 #define	XHCI_HCS0_PIND(x)	(((x) >> 4) & 0x1)	/* port indicators */  argument
67 #define	XHCI_HCS0_LHRC(x)	(((x) >> 5) & 0x1)	/* light HC reset */  argument
68 #define	XHCI_HCS0_LTC(x)	(((x) >> 6) & 0x1)	/* latency tolerance msg */  argument
69 #define	XHCI_HCS0_NSS(x)	(((x) >> 7) & 0x1)	/* no secondary sid */  argument
70 #define	XHCI_HCS0_PSA_SZ_MAX(x)	(((x) >> 12) & 0xF)	/* max pri. stream array size */  argument
71 #define	XHCI_HCS0_XECP(x)	(((x) >> 16) & 0xFFFF)	/* extended capabilities pointer */  argument
122 #define	XHCI_PS_PLS_GET(x)	(((x) >> 5) & 0xF)	/* RW - port link state */  argument
123 #define	XHCI_PS_PLS_SET(x)	(((x) & 0xF) << 5)	/* RW - port link state */  argument
125 #define	XHCI_PS_SPEED_GET(x)	(((x) >> 10) & 0xF)	/* RO - port speed */  argument
130 #define	XHCI_PS_PIC_GET(x)	(((x) >> 14) & 0x3)	/* RW - port indicator */  argument
131 #define	XHCI_PS_PIC_SET(x)	(((x) & 0x3) << 14)	/* RW - port indicator */  argument
149 #define	XHCI_PM3_U1TO_GET(x)	(((x) >> 0) & 0xFF)	/* RW - U1 timeout */  argument
150 #define	XHCI_PM3_U1TO_SET(x)	(((x) & 0xFF) << 0)	/* RW - U1 timeout */  argument
151 #define	XHCI_PM3_U2TO_GET(x)	(((x) >> 8) & 0xFF)	/* RW - U2 timeout */  argument
152 #define	XHCI_PM3_U2TO_SET(x)	(((x) & 0xFF) << 8)	/* RW - U2 timeout */  argument
154 #define	XHCI_PM2_L1S_GET(x)	(((x) >> 0) & 0x7)	/* RO - L1 status */  argument
156 #define	XHCI_PM2_HIRD_GET(x)	(((x) >> 4) & 0xF)	/* RW - host initiated resume duration */  argument
157 #define	XHCI_PM2_HIRD_SET(x)	(((x) & 0xF) << 4)	/* RW - host initiated resume duration */  argument
158 #define	XHCI_PM2_L1SLOT_GET(x)	(((x) >> 8) & 0xFF)	/* RW - L1 device slot */  argument
159 #define	XHCI_PM2_L1SLOT_SET(x)	(((x) & 0xFF) << 8)	/* RW - L1 device slot */  argument
162 #define	XHCI_PLI3_ERR_GET(x)	(((x) >> 0) & 0xFFFF)	/* RO - port link errors */  argument
167 #define	XHCI_MFINDEX_GET(x)	((x) & 0x3FFF)  argument
172 #define	XHCI_IMOD_IVAL_GET(x)	(((x) >> 0) & 0xFFFF)	/* 250ns unit */  argument
173 #define	XHCI_IMOD_IVAL_SET(x)	(((x) & 0xFFFF) << 0)	/* 250ns unit */  argument
174 #define	XHCI_IMOD_ICNT_GET(x)	(((x) >> 16) & 0xFFFF)	/* 250ns unit */  argument
175 #define	XHCI_IMOD_ICNT_SET(x)	(((x) & 0xFFFF) << 16)	/* 250ns unit */  argument
179 #define	XHCI_ERSTS_GET(x)	((x) & 0xFFFF)  argument
180 #define	XHCI_ERSTS_SET(x)	((x) & 0xFFFF)  argument
184 #define	XHCI_ERDP_LO_SINDEX(x)	((x) & 0x7)	/* RO - dequeue segment index */  argument
190 #define	XHCI_DB_TARGET_GET(x)	((x) & 0xFF)		/* RW - doorbell target */  argument
191 #define	XHCI_DB_TARGET_SET(x)	((x) & 0xFF)		/* RW - doorbell target */  argument
192 #define	XHCI_DB_SID_GET(x)	(((x) >> 16) & 0xFFFF)	/* RW - doorbell stream ID */  argument
193 #define	XHCI_DB_SID_SET(x)	(((x) & 0xFFFF) << 16)	/* RW - doorbell stream ID */  argument
196 #define	XHCI_XECP_ID(x)		((x) & 0xFF)  argument
197 #define	XHCI_XECP_NEXT(x)	(((x) >> 8) & 0xFF)  argument
219 #define	XWRITE1(sc, what, a, x) \  argument
221 		(a) + (sc)->sc_##what##_off, (x))
222 #define	XWRITE2(sc, what, a, x) \  argument
224 		(a) + (sc)->sc_##what##_off, (x))
225 #define	XWRITE4(sc, what, a, x) \  argument
227 		(a) + (sc)->sc_##what##_off, (x))