Lines Matching full:xhci

32 /* XHCI PCI config registers */
43 /* XHCI capability registers */
47 #define	XHCI_HCIVERSION_0_9	0x0090	/* xHCI version 0.9 */
48 #define	XHCI_HCIVERSION_1_0	0x0100	/* xHCI version 1.0 */
75 /* XHCI operational registers.  Offset given by XHCI_CAPLENGTH register */
76 #define	XHCI_USBCMD		0x00	/* XHCI command */
86 #define	XHCI_USBSTS		0x04	/* XHCI status */
96 #define	XHCI_PAGESIZE		0x08	/* XHCI page size mask */
102 #define	XHCI_DNCTRL		0x14	/* XHCI device notification control */
104 #define	XHCI_CRCR_LO		0x18	/* XHCI command ring control */
110 #define	XHCI_CRCR_HI		0x1C	/* XHCI command ring control */
111 #define	XHCI_DCBAAP_LO		0x30	/* XHCI dev context BA pointer */
112 #define	XHCI_DCBAAP_HI		0x34	/* XHCI dev context BA pointer */
116 /* XHCI port status registers */
117 #define	XHCI_PORTSC(n)		(0x3F0 + (0x10 * (n)))	/* XHCI port status */
148 #define	XHCI_PORTPMSC(n)	(0x3F4 + (0x10 * (n)))	/* XHCI status and control */
161 #define	XHCI_PORTLI(n)		(0x3F8 + (0x10 * (n)))	/* XHCI port link info */
163 #define	XHCI_PORTRSV(n)		(0x3FC + (0x10 * (n)))	/* XHCI port reserved */
165 /* XHCI runtime registers.  Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */
168 #define	XHCI_IMAN(n)		(0x0020 + (0x20 * (n)))	/* XHCI interrupt management */
171 #define	XHCI_IMOD(n)		(0x0024 + (0x20 * (n)))	/* XHCI interrupt moderation */
178 #define	XHCI_ERSTSZ(n)		(0x0028 + (0x20 * (n)))	/* XHCI event ring segment table size */
181 #define	XHCI_ERSTBA_LO(n)	(0x0030 + (0x20 * (n)))	/* XHCI event ring segment table BA */
182 #define	XHCI_ERSTBA_HI(n)	(0x0034 + (0x20 * (n)))	/* XHCI event ring segment table BA */
183 #define	XHCI_ERDP_LO(n)	(0x0038 + (0x20 * (n)))	/* XHCI event ring dequeue pointer */
186 #define	XHCI_ERDP_HI(n)	(0x003C + (0x20 * (n)))	/* XHCI event ring dequeue pointer */
188 /* XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */
195 /* XHCI legacy support */
201 /* XHCI capability ID's */
209 /* XHCI register R/W wrappers */