Lines Matching +full:usb2 +full:- +full:lpm +full:- +full:disable
2 /*-
3 * SPDX-License-Identifier: BSD-2-Clause
38 #define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */
39 #define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */
62 #define XHCI_HCS0_AC64(x) ((x) & 0x1) /* 64-bit capable */
87 #define XHCI_STS_HCH 0x00000001 /* RO - Host Controller Halted */
88 #define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */
89 #define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */
90 #define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */
91 #define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */
92 #define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */
93 #define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */
94 #define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */
95 #define XHCI_STS_HCE 0x00001000 /* RO - Host Controller Error */
105 #define XHCI_CRCR_LO_RCS 0x00000001 /* RW - consumer cycle state */
106 #define XHCI_CRCR_LO_CS 0x00000002 /* RW - command stop */
107 #define XHCI_CRCR_LO_CA 0x00000004 /* RW - command abort */
108 #define XHCI_CRCR_LO_CRR 0x00000008 /* RW - command ring running */
114 #define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slots enabled */
118 #define XHCI_PS_CCS 0x00000001 /* RO - current connect status */
119 #define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */
120 #define XHCI_PS_OCA 0x00000008 /* RO - over current active */
121 #define XHCI_PS_PR 0x00000010 /* RW - port reset */
122 #define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */
123 #define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */
124 #define XHCI_PS_PP 0x00000200 /* RW - port power */
125 #define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */
130 #define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */
131 #define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */
132 #define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */
133 #define XHCI_PS_CSC 0x00020000 /* RW - connect status change */
134 #define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */
135 #define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */
136 #define XHCI_PS_OCC 0x00100000 /* RW - over-current change */
137 #define XHCI_PS_PRC 0x00200000 /* RW - port reset change */
138 #define XHCI_PS_PLC 0x00400000 /* RW - port link state change */
139 #define XHCI_PS_CEC 0x00800000 /* RW - config error change */
140 #define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */
141 #define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */
142 #define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */
143 #define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */
144 #define XHCI_PS_DR 0x40000000 /* RO - device removable */
145 #define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */
149 #define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */
150 #define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */
151 #define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */
152 #define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */
153 #define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */
154 #define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */
155 #define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */
156 #define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) /* RW - host initiated resume duration */
157 #define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) /* RW - host initiated resume duration */
158 #define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */
159 #define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */
160 #define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */
162 #define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errors */
166 #define XHCI_MFINDEX 0x0000 /* RO - microframe index */
169 #define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */
170 #define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */
177 #define XHCI_IMOD_DEFAULT_LP 0x000003F8U /* 4000 IRQs/second - LynxPoint */
184 #define XHCI_ERDP_LO_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */
185 #define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */
190 #define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */
191 #define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */
192 #define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */
193 #define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) /* RW - doorbell stream ID */
211 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \
212 (a) + (sc)->sc_##what##_off)
214 bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \
215 (a) + (sc)->sc_##what##_off)
217 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \
218 (a) + (sc)->sc_##what##_off)
220 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \
221 (a) + (sc)->sc_##what##_off, (x))
223 bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \
224 (a) + (sc)->sc_##what##_off, (x))
226 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \
227 (a) + (sc)->sc_##what##_off, (x))