Lines Matching full:rw
36 #define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */
77 #define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */
78 #define XHCI_CMD_HCRST 0x00000002 /* RW Host Controller Reset */
79 #define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */
80 #define XHCI_CMD_HSEE 0x00000008 /* RW Host System Error Enable */
81 #define XHCI_CMD_LHCRST 0x00000080 /* RO/RW Light Host Controller Reset */
82 #define XHCI_CMD_CSS 0x00000100 /* RW Controller Save State */
83 #define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore State */
84 #define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */
85 #define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */
88 #define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */
89 #define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */
90 #define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */
93 #define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */
105 #define XHCI_CRCR_LO_RCS 0x00000001 /* RW - consumer cycle state */
106 #define XHCI_CRCR_LO_CS 0x00000002 /* RW - command stop */
107 #define XHCI_CRCR_LO_CA 0x00000004 /* RW - command abort */
108 #define XHCI_CRCR_LO_CRR 0x00000008 /* RW - command ring running */
114 #define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slots enabled */
119 #define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */
121 #define XHCI_PS_PR 0x00000010 /* RW - port reset */
122 #define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */
123 #define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */
124 #define XHCI_PS_PP 0x00000200 /* RW - port power */
130 #define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */
131 #define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */
132 #define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */
133 #define XHCI_PS_CSC 0x00020000 /* RW - connect status change */
134 #define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */
135 #define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */
136 #define XHCI_PS_OCC 0x00100000 /* RW - over-current change */
137 #define XHCI_PS_PRC 0x00200000 /* RW - port reset change */
138 #define XHCI_PS_PLC 0x00400000 /* RW - port link state change */
139 #define XHCI_PS_CEC 0x00800000 /* RW - config error change */
141 #define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */
142 #define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */
143 #define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */
145 #define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */
149 #define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */
150 #define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */
151 #define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */
152 #define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */
153 #define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */
155 #define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */
156 #define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) /* RW - host initiated resume duration */
157 #define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) /* RW - host initiated resume duration */
158 #define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */
159 #define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */
160 #define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */
169 #define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */
170 #define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */
185 #define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */
190 #define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */
191 #define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */
192 #define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */
193 #define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) /* RW - doorbell stream ID */