Lines Matching refs:XWRITE4
262 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); in xhci_reset_command_queue_locked()
263 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); in xhci_reset_command_queue_locked()
265 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); in xhci_reset_command_queue_locked()
266 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); in xhci_reset_command_queue_locked()
297 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); in xhci_reset_command_queue_locked()
298 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); in xhci_reset_command_queue_locked()
329 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); in xhci_start_controller()
334 XWRITE4(sc, oper, XHCI_USBSTS, temp); in xhci_start_controller()
336 XWRITE4(sc, oper, XHCI_DNCTRL, 0); in xhci_start_controller()
357 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); in xhci_start_controller()
358 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); in xhci_start_controller()
359 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); in xhci_start_controller()
360 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); in xhci_start_controller()
366 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); in xhci_start_controller()
369 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); in xhci_start_controller()
398 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); in xhci_start_controller()
399 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); in xhci_start_controller()
405 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); in xhci_start_controller()
406 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); in xhci_start_controller()
411 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_start_controller()
419 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); in xhci_start_controller()
420 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); in xhci_start_controller()
427 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | in xhci_start_controller()
437 XWRITE4(sc, oper, XHCI_USBCMD, 0); in xhci_start_controller()
467 XWRITE4(sc, oper, XHCI_USBCMD, 0); in xhci_halt_controller()
492 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); in xhci_reset_controller()
1195 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); in xhci_interrupt_poll()
1196 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); in xhci_interrupt_poll()
1281 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); in xhci_do_command()
1697 XWRITE4(sc, oper, XHCI_USBSTS, status); in xhci_interrupt()
1705 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_interrupt()
2889 XWRITE4(sc, door, XHCI_DOORBELL(index), in xhci_endpoint_doorbell()
3456 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); in xhci_roothub_exec()
3459 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); in xhci_roothub_exec()
3463 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); in xhci_roothub_exec()
3466 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); in xhci_roothub_exec()
3469 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); in xhci_roothub_exec()
3472 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); in xhci_roothub_exec()
3475 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); in xhci_roothub_exec()
3479 XWRITE4(sc, oper, port, v | XHCI_PS_PED); in xhci_roothub_exec()
3482 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); in xhci_roothub_exec()
3485 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); in xhci_roothub_exec()
3491 XWRITE4(sc, oper, port, v | in xhci_roothub_exec()
3499 XWRITE4(sc, oper, port, v | in xhci_roothub_exec()
3645 XWRITE4(sc, oper, port, v); in xhci_roothub_exec()
3656 XWRITE4(sc, oper, port, v); in xhci_roothub_exec()
3659 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); in xhci_roothub_exec()
3662 XWRITE4(sc, oper, port, v | in xhci_roothub_exec()
3678 XWRITE4(sc, oper, port, v | in xhci_roothub_exec()
3683 XWRITE4(sc, oper, port, v | XHCI_PS_PR); in xhci_roothub_exec()
3687 XWRITE4(sc, oper, port, v | XHCI_PS_PP); in xhci_roothub_exec()
3698 XWRITE4(sc, oper, port, v); in xhci_roothub_exec()
4308 XWRITE4(sc, door, XHCI_DOORBELL(index), in xhci_device_resume()