Lines Matching full:temp
246 uint32_t temp; in xhci_reset_command_queue_locked() local
250 temp = XREAD4(sc, oper, XHCI_CRCR_LO); in xhci_reset_command_queue_locked()
251 if (temp & XHCI_CRCR_LO_CRR) { in xhci_reset_command_queue_locked()
253 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); in xhci_reset_command_queue_locked()
262 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); in xhci_reset_command_queue_locked()
265 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); in xhci_reset_command_queue_locked()
272 temp = XREAD4(sc, oper, XHCI_CRCR_LO); in xhci_reset_command_queue_locked()
273 if (temp & XHCI_CRCR_LO_CRR) { in xhci_reset_command_queue_locked()
311 uint32_t temp; in xhci_start_controller() local
331 temp = XREAD4(sc, oper, XHCI_USBSTS); in xhci_start_controller()
334 XWRITE4(sc, oper, XHCI_USBSTS, temp); in xhci_start_controller()
409 temp = XREAD4(sc, runt, XHCI_IMAN(0)); in xhci_start_controller()
410 temp |= XHCI_IMAN_INTR_ENA; in xhci_start_controller()
411 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_start_controller()
432 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; in xhci_start_controller()
433 if (!temp) in xhci_start_controller()
436 if (temp) { in xhci_start_controller()
456 uint32_t temp; in xhci_halt_controller() local
471 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; in xhci_halt_controller()
472 if (temp) in xhci_halt_controller()
476 if (!temp) { in xhci_halt_controller()
486 uint32_t temp = 0; in xhci_reset_controller() local
496 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | in xhci_reset_controller()
498 if (!temp) in xhci_reset_controller()
502 if (temp) { in xhci_reset_controller()
513 uint32_t temp; in xhci_init() local
552 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); in xhci_init()
554 DPRINTF("HCS0 = 0x%08x\n", temp); in xhci_init()
557 if (XHCI_HCS0_CSZ(temp)) { in xhci_init()
564 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && in xhci_init()
575 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); in xhci_init()
578 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); in xhci_init()
586 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); in xhci_init()
593 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); in xhci_init()
595 DPRINTF("HCS2=0x%08x\n", temp); in xhci_init()
598 sc->sc_ist = XHCI_HCS2_IST(temp); in xhci_init()
601 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); in xhci_init()
612 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); in xhci_init()
616 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); in xhci_init()
619 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + in xhci_init()
620 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; in xhci_init()
942 uint32_t temp; in xhci_check_transfer() local
953 temp = le32toh(trb->dwTrb2); in xhci_check_transfer()
955 remainder = XHCI_TRB_2_REM_GET(temp); in xhci_check_transfer()
956 status = XHCI_TRB_2_ERROR_GET(temp); in xhci_check_transfer()
958 temp = le32toh(trb->dwTrb3); in xhci_check_transfer()
959 epno = XHCI_TRB_3_EP_GET(temp); in xhci_check_transfer()
960 index = XHCI_TRB_3_SLOT_GET(temp); in xhci_check_transfer()
1024 temp = le32toh(td->td_trb[i].dwTrb2); in xhci_check_transfer()
1025 remainder += XHCI_TRB_2_BYTES_GET(temp); in xhci_check_transfer()
1120 uint32_t temp; in xhci_interrupt_poll() local
1141 temp = le32toh(phwr->hwr_events[i].dwTrb3); in xhci_interrupt_poll()
1143 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; in xhci_interrupt_poll()
1148 event = XHCI_TRB_3_TYPE_GET(temp); in xhci_interrupt_poll()
1208 uint32_t temp; in xhci_do_command() local
1240 temp = trb->dwTrb3; in xhci_do_command()
1243 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); in xhci_do_command()
1245 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); in xhci_do_command()
1247 temp &= ~htole32(XHCI_TRB_3_TC_BIT); in xhci_do_command()
1249 phwr->hwr_commands[i].dwTrb3 = temp; in xhci_do_command()
1262 temp = htole32(XHCI_TRB_3_TC_BIT | in xhci_do_command()
1266 temp = htole32(XHCI_TRB_3_TC_BIT | in xhci_do_command()
1270 phwr->hwr_commands[i].dwTrb3 = temp; in xhci_do_command()
1306 temp = le32toh(trb->dwTrb3); in xhci_do_command()
1313 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && in xhci_do_command()
1314 (temp & XHCI_TRB_3_BSR_BIT) == 0) { in xhci_do_command()
1328 temp = le32toh(sc->sc_cmd_result[0]); in xhci_do_command()
1329 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) in xhci_do_command()
1346 uint32_t temp;
1352 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1354 trb.dwTrb3 = htole32(temp);
1364 uint32_t temp; in xhci_cmd_enable_slot() local
1377 temp = le32toh(trb.dwTrb3); in xhci_cmd_enable_slot()
1379 *pslot = XHCI_TRB_3_SLOT_GET(temp); in xhci_cmd_enable_slot()
1389 uint32_t temp; in xhci_cmd_disable_slot() local
1395 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | in xhci_cmd_disable_slot()
1398 trb.dwTrb3 = htole32(temp); in xhci_cmd_disable_slot()
1408 uint32_t temp; in xhci_cmd_set_address() local
1414 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | in xhci_cmd_set_address()
1418 temp |= XHCI_TRB_3_BSR_BIT; in xhci_cmd_set_address()
1420 trb.dwTrb3 = htole32(temp); in xhci_cmd_set_address()
1434 uint32_t temp; in xhci_set_address() local
1508 temp = le32toh(sc->sc_cmd_result[0]); in xhci_set_address()
1510 XHCI_TRB_2_ERROR_GET(temp) == in xhci_set_address()
1529 temp = le32toh(slot->dwSctx3); in xhci_set_address()
1530 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); in xhci_set_address()
1558 uint32_t temp; in xhci_cmd_configure_ep() local
1564 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | in xhci_cmd_configure_ep()
1570 temp |= XHCI_TRB_3_DCEP_BIT; in xhci_cmd_configure_ep()
1573 trb.dwTrb3 = htole32(temp); in xhci_cmd_configure_ep()
1583 uint32_t temp; in xhci_cmd_evaluate_ctx() local
1589 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | in xhci_cmd_evaluate_ctx()
1591 trb.dwTrb3 = htole32(temp); in xhci_cmd_evaluate_ctx()
1601 uint32_t temp; in xhci_cmd_reset_ep() local
1607 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | in xhci_cmd_reset_ep()
1612 temp |= XHCI_TRB_3_PRSV_BIT; in xhci_cmd_reset_ep()
1614 trb.dwTrb3 = htole32(temp); in xhci_cmd_reset_ep()
1624 uint32_t temp; in xhci_cmd_set_tr_dequeue_ptr() local
1630 temp = XHCI_TRB_2_STREAM_SET(stream_id); in xhci_cmd_set_tr_dequeue_ptr()
1631 trb.dwTrb2 = htole32(temp); in xhci_cmd_set_tr_dequeue_ptr()
1633 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | in xhci_cmd_set_tr_dequeue_ptr()
1636 trb.dwTrb3 = htole32(temp); in xhci_cmd_set_tr_dequeue_ptr()
1646 uint32_t temp; in xhci_cmd_stop_ep() local
1652 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | in xhci_cmd_stop_ep()
1657 temp |= XHCI_TRB_3_SUSP_EP_BIT; in xhci_cmd_stop_ep()
1659 trb.dwTrb3 = htole32(temp); in xhci_cmd_stop_ep()
1668 uint32_t temp; in xhci_cmd_reset_dev() local
1674 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | in xhci_cmd_reset_dev()
1677 trb.dwTrb3 = htole32(temp); in xhci_cmd_reset_dev()
1689 uint32_t temp; in xhci_interrupt() local
1701 temp = XREAD4(sc, runt, XHCI_IMAN(0)); in xhci_interrupt()
1704 if (temp & XHCI_IMAN_INTR_PEND) in xhci_interrupt()
1705 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_interrupt()
1761 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) in xhci_setup_generic_chain_sub() argument
1779 shortpkt_old = temp->shortpkt; in xhci_setup_generic_chain_sub()
1780 len_old = temp->len; in xhci_setup_generic_chain_sub()
1786 td = temp->td; in xhci_setup_generic_chain_sub()
1787 td_next = td_first = temp->td_next; in xhci_setup_generic_chain_sub()
1790 if (temp->len == 0) { in xhci_setup_generic_chain_sub()
1791 if (temp->shortpkt) in xhci_setup_generic_chain_sub()
1796 temp->shortpkt = 1; in xhci_setup_generic_chain_sub()
1800 average = temp->average; in xhci_setup_generic_chain_sub()
1802 if (temp->len < average) { in xhci_setup_generic_chain_sub()
1803 if (temp->len % temp->max_packet_size) { in xhci_setup_generic_chain_sub()
1804 temp->shortpkt = 1; in xhci_setup_generic_chain_sub()
1806 average = temp->len; in xhci_setup_generic_chain_sub()
1823 temp->len -= average; in xhci_setup_generic_chain_sub()
1835 temp->len -= average; in xhci_setup_generic_chain_sub()
1841 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { in xhci_setup_generic_chain_sub()
1849 usbd_copy_out(temp->pc, temp->offset + buf_offset, in xhci_setup_generic_chain_sub()
1886 usbd_get_page(temp->pc, temp->offset + in xhci_setup_generic_chain_sub()
1902 temp->max_packet_size); in xhci_setup_generic_chain_sub()
1920 switch (temp->trb_type) { in xhci_setup_generic_chain_sub()
1923 XHCI_TRB_3_TBC_SET(temp->tbc) | in xhci_setup_generic_chain_sub()
1924 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); in xhci_setup_generic_chain_sub()
1927 } else if (temp->do_isoc_sync != 0) { in xhci_setup_generic_chain_sub()
1928 temp->do_isoc_sync = 0; in xhci_setup_generic_chain_sub()
1931 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); in xhci_setup_generic_chain_sub()
1937 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1943 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1953 temp->trb_type = XHCI_TRB_TYPE_NORMAL; in xhci_setup_generic_chain_sub()
1958 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1964 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
2027 if (temp->last_frame) { in xhci_setup_generic_chain_sub()
2035 temp->shortpkt = shortpkt_old; in xhci_setup_generic_chain_sub()
2036 temp->len = len_old; in xhci_setup_generic_chain_sub()
2044 if (temp->step_td != 0) { in xhci_setup_generic_chain_sub()
2058 temp->td = td; in xhci_setup_generic_chain_sub()
2059 temp->td_next = td_next; in xhci_setup_generic_chain_sub()
2065 struct xhci_std_temp temp; in xhci_setup_generic_chain() local
2071 temp.do_isoc_sync = 0; in xhci_setup_generic_chain()
2072 temp.step_td = 0; in xhci_setup_generic_chain()
2073 temp.tbc = 0; in xhci_setup_generic_chain()
2074 temp.tlbpc = 0; in xhci_setup_generic_chain()
2075 temp.average = xfer->max_hc_frame_size; in xhci_setup_generic_chain()
2076 temp.max_packet_size = xfer->max_packet_size; in xhci_setup_generic_chain()
2077 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); in xhci_setup_generic_chain()
2078 temp.pc = NULL; in xhci_setup_generic_chain()
2079 temp.last_frame = 0; in xhci_setup_generic_chain()
2080 temp.offset = 0; in xhci_setup_generic_chain()
2081 temp.multishort = xfer->flags_int.isochronous_xfr || in xhci_setup_generic_chain()
2091 temp.td = NULL; in xhci_setup_generic_chain()
2092 temp.td_next = td; in xhci_setup_generic_chain()
2115 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); in xhci_setup_generic_chain()
2117 DPRINTF("MFINDEX=0x%08x IST=0x%x\n", x, temp.sc->sc_ist); in xhci_setup_generic_chain()
2122 temp.isoc_delta = 8; /* 1ms */ in xhci_setup_generic_chain()
2126 temp.isoc_delta = 1U << shift; in xhci_setup_generic_chain()
2131 if (temp.sc->sc_ist & 8) in xhci_setup_generic_chain()
2132 y = (temp.sc->sc_ist & 7) << 3; in xhci_setup_generic_chain()
2134 y = (temp.sc->sc_ist & 7); in xhci_setup_generic_chain()
2140 DPRINTFN(3, "IST(%d) is too big!\n", temp.sc->sc_ist); in xhci_setup_generic_chain()
2159 xfer, x, y, 8, XHCI_MFINDEX_GET(-1), &temp.isoc_frame)) { in xhci_setup_generic_chain()
2161 temp.do_isoc_sync = 1; in xhci_setup_generic_chain()
2163 DPRINTFN(3, "start next=%d\n", temp.isoc_frame); in xhci_setup_generic_chain()
2167 temp.trb_type = XHCI_TRB_TYPE_ISOCH; in xhci_setup_generic_chain()
2173 temp.len = xfer->frlengths[0]; in xhci_setup_generic_chain()
2174 temp.pc = xfer->frbuffers + 0; in xhci_setup_generic_chain()
2175 temp.shortpkt = temp.len ? 1 : 0; in xhci_setup_generic_chain()
2176 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; in xhci_setup_generic_chain()
2177 temp.direction = 0; in xhci_setup_generic_chain()
2183 temp.last_frame = 1; in xhci_setup_generic_chain()
2186 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2190 temp.isoc_delta = 0; in xhci_setup_generic_chain()
2191 temp.isoc_frame = 0; in xhci_setup_generic_chain()
2192 temp.trb_type = xfer->flags_int.control_did_data ? in xhci_setup_generic_chain()
2197 temp.isoc_delta = 0; in xhci_setup_generic_chain()
2198 temp.isoc_frame = 0; in xhci_setup_generic_chain()
2199 temp.trb_type = XHCI_TRB_TYPE_NORMAL; in xhci_setup_generic_chain()
2204 temp.pc = xfer->frbuffers + x; in xhci_setup_generic_chain()
2206 temp.direction = UE_GET_DIR(xfer->endpointno); in xhci_setup_generic_chain()
2212 temp.len = xfer->frlengths[x]; in xhci_setup_generic_chain()
2213 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && in xhci_setup_generic_chain()
2214 x != 0 && temp.multishort == 0); in xhci_setup_generic_chain()
2222 temp.last_frame = 1; in xhci_setup_generic_chain()
2224 temp.last_frame = 1; in xhci_setup_generic_chain()
2227 if (temp.len == 0) { in xhci_setup_generic_chain()
2230 temp.shortpkt = 0; in xhci_setup_generic_chain()
2232 temp.tbc = 0; in xhci_setup_generic_chain()
2233 temp.tlbpc = mult - 1; in xhci_setup_generic_chain()
2243 temp.shortpkt = 1; in xhci_setup_generic_chain()
2247 if (temp.len > xfer->max_frame_size) in xhci_setup_generic_chain()
2248 temp.len = xfer->max_frame_size; in xhci_setup_generic_chain()
2251 tdpc = howmany(temp.len, xfer->max_packet_size); in xhci_setup_generic_chain()
2253 temp.tbc = howmany(tdpc, mult) - 1; in xhci_setup_generic_chain()
2254 temp.tlbpc = (tdpc % mult); in xhci_setup_generic_chain()
2256 if (temp.tlbpc == 0) in xhci_setup_generic_chain()
2257 temp.tlbpc = mult - 1; in xhci_setup_generic_chain()
2259 temp.tlbpc--; in xhci_setup_generic_chain()
2263 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; in xhci_setup_generic_chain()
2266 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2269 temp.offset += xfer->frlengths[x - 1]; in xhci_setup_generic_chain()
2270 temp.isoc_frame += temp.isoc_delta; in xhci_setup_generic_chain()
2273 temp.pc = xfer->frbuffers + x; in xhci_setup_generic_chain()
2285 if (xhcictlstep || temp.sc->sc_ctlstep) { in xhci_setup_generic_chain()
2292 temp.step_td = (xfer->nframes != 0); in xhci_setup_generic_chain()
2294 temp.step_td = 0; in xhci_setup_generic_chain()
2296 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; in xhci_setup_generic_chain()
2297 temp.len = 0; in xhci_setup_generic_chain()
2298 temp.pc = NULL; in xhci_setup_generic_chain()
2299 temp.shortpkt = 0; in xhci_setup_generic_chain()
2300 temp.last_frame = 1; in xhci_setup_generic_chain()
2301 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; in xhci_setup_generic_chain()
2303 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2306 td = temp.td; in xhci_setup_generic_chain()
2339 uint32_t temp; in xhci_configure_mask() local
2381 temp = le32toh(slot->dwSctx0); in xhci_configure_mask()
2382 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); in xhci_configure_mask()
2383 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); in xhci_configure_mask()
2384 slot->dwSctx0 = htole32(temp); in xhci_configure_mask()
2401 uint32_t temp; in xhci_configure_endpoint() local
2439 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | in xhci_configure_endpoint()
2446 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | in xhci_configure_endpoint()
2467 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); in xhci_configure_endpoint()
2470 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); in xhci_configure_endpoint()
2476 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); in xhci_configure_endpoint()
2487 endp->dwEpCtx0 = htole32(temp); in xhci_configure_endpoint()
2489 temp = in xhci_configure_endpoint()
2501 temp |= XHCI_EPCTX_1_CERR_SET(3); in xhci_configure_endpoint()
2505 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); in xhci_configure_endpoint()
2508 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); in xhci_configure_endpoint()
2511 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); in xhci_configure_endpoint()
2514 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); in xhci_configure_endpoint()
2520 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); in xhci_configure_endpoint()
2522 endp->dwEpCtx1 = htole32(temp); in xhci_configure_endpoint()
2528 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | in xhci_configure_endpoint()
2533 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); in xhci_configure_endpoint()
2536 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); in xhci_configure_endpoint()
2540 endp->dwEpCtx4 = htole32(temp); in xhci_configure_endpoint()
2563 uint64_t temp; in xhci_configure_endpoint_by_xfer() local
2569 temp = pepext->physaddr + in xhci_configure_endpoint_by_xfer()
2575 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); in xhci_configure_endpoint_by_xfer()
2601 uint32_t temp; in xhci_configure_device() local
2648 temp = XHCI_SCTX_0_ROUTE_SET(route) | in xhci_configure_device()
2654 temp |= XHCI_SCTX_0_SPEED_SET(2); in xhci_configure_device()
2659 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2663 temp |= XHCI_SCTX_0_SPEED_SET(3); in xhci_configure_device()
2667 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2671 temp |= XHCI_SCTX_0_SPEED_SET(1); in xhci_configure_device()
2676 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2680 temp |= XHCI_SCTX_0_SPEED_SET(4); in xhci_configure_device()
2689 temp |= XHCI_SCTX_0_HUB_SET(1); in xhci_configure_device()
2691 slot->dwSctx0 = htole32(temp); in xhci_configure_device()
2693 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); in xhci_configure_device()
2696 temp |= XHCI_SCTX_1_NUM_PORTS_SET( in xhci_configure_device()
2700 slot->dwSctx1 = htole32(temp); in xhci_configure_device()
2702 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); in xhci_configure_device()
2705 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( in xhci_configure_device()
2716 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( in xhci_configure_device()
2718 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( in xhci_configure_device()
2726 slot->dwSctx2 = htole32(temp); in xhci_configure_device()
2732 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | in xhci_configure_device()
2735 slot->dwSctx3 = htole32(temp); in xhci_configure_device()
3339 sc->sc_hub_desc.temp[0] = sc->sc_conf; in xhci_roothub_exec()
3390 sc->sc_hub_desc.temp, in xhci_roothub_exec()
3391 sizeof(sc->sc_hub_desc.temp), in xhci_roothub_exec()
3402 sc->sc_hub_desc.temp[0] = 0; in xhci_roothub_exec()
3547 memset(sc->sc_hub_desc.temp, 0, 16); in xhci_roothub_exec()
3829 uint32_t temp; in xhci_get_endpoint_state() local
3840 temp = le32toh(endp->dwEpCtx0); in xhci_get_endpoint_state()
3842 return (XHCI_EPCTX_0_EPSTATE_GET(temp)); in xhci_get_endpoint_state()
4189 uint8_t temp; in xhci_device_init() local
4203 err = xhci_cmd_enable_slot(sc, &temp); in xhci_device_init()
4210 if (temp > sc->sc_noslot) { in xhci_device_init()
4215 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { in xhci_device_init()
4216 DPRINTF("slot %u already allocated.\n", temp); in xhci_device_init()
4223 udev->controller_slot_id = temp; in xhci_device_init()
4227 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); in xhci_device_init()
4231 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; in xhci_device_init()