Lines Matching +full:disable +full:- +full:port +full:- +full:power +full:- +full:control
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 #define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */
59 * (least-significant byte) and
70 #define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */
78 #define EHCI_HCSP_PORTROUTE 0x0c /* RO Companion port route description */
109 #define EHCI_STS_PCD 0x00000004 /* RWC port change detect */
126 #define EHCI_INTR_PCIE 0x00000004 /* port change ena */
132 #define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */
140 #define EHCI_PORTSC(n) (0x40+(4*(n))) /* RO, RW, RWC Port Status reg */
144 #define EHCI_PS_PTC 0x000f0000 /* RW port test control */
145 #define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */
146 #define EHCI_PS_PO 0x00002000 /* RW port owner */
147 #define EHCI_PS_PP 0x00001000 /* RW,RO port power */
150 #define EHCI_PS_PR 0x00000100 /* RW port reset */
152 #define EHCI_PS_FPR 0x00000040 /* RW force port resume */
155 #define EHCI_PS_PEC 0x00000008 /* RWC port enable change */
156 #define EHCI_PS_PE 0x00000004 /* RW port enable */
176 #define EHCI_UM_ES_LE 0x0 /* Little-endian byte alignment */
177 #define EHCI_UM_ES_BE 0x4 /* Big-endian byte alignment */
178 #define EHCI_UM_SDIS 0x00000010 /* R/WO Stream Disable Mode */
181 * Actual port speed bits depends on EHCI_HOSTC(n) registers presence,
184 #define EHCI_HOSTC(n) (0x80+(4*(n))) /* RO, RW Host mode control reg */