Lines Matching full:rw

44 #define	PCI_EHCI_FLADJ		0x61	/* RW Frame len adj, SOF=59488+6*fladj */
45 #define	PCI_EHCI_PORTWAKECAP	0x62	/* RW Port wake caps (opt)  */
81 #define	EHCI_USBCMD		0x00	/* RO, RW, WO Command register */
82 #define	EHCI_CMD_ITC_M		0x00ff0000	/* RW interrupt threshold ctrl */
90 #define	EHCI_CMD_ASPME		0x00000800	/* RW/RO async park enable */
91 #define	EHCI_CMD_ASPMC		0x00000300	/* RW/RO async park count */
92 #define	EHCI_CMD_LHCR		0x00000080	/* RW light host ctrl reset */
93 #define	EHCI_CMD_IAAD		0x00000040	/* RW intr on async adv door
95 #define	EHCI_CMD_ASE		0x00000020	/* RW async sched enable */
96 #define	EHCI_CMD_PSE		0x00000010	/* RW periodic sched enable */
97 #define	EHCI_CMD_FLS_M		0x0000000c	/* RW/RO frame list size */
98 #define	EHCI_CMD_FLS(x)		(((x) >> 2) & 3)	/* RW/RO frame list size */
99 #define	EHCI_CMD_HCRESET	0x00000002	/* RW reset */
100 #define	EHCI_CMD_RS		0x00000001	/* RW run/stop */
101 #define	EHCI_USBSTS		0x04	/* RO, RW, RWC Status register */
121 #define	EHCI_USBINTR		0x08	/* RW Interrupt register */
130 #define	EHCI_FRINDEX		0x0c	/* RW Frame Index register */
132 #define	EHCI_CTRLDSSEGMENT	0x10	/* RW Control Data Structure Segment */
134 #define	EHCI_PERIODICLISTBASE	0x14	/* RW Periodic List Base */
135 #define	EHCI_ASYNCLISTADDR	0x18	/* RW Async List Base */
137 #define	EHCI_CONFIGFLAG		0x40	/* RW Configure Flag register */
138 #define	EHCI_CONF_CF		0x00000001	/* RW configure flag */
140 #define	EHCI_PORTSC(n)		(0x40+(4*(n)))	/* RO, RW, RWC Port Status reg */
141 #define	EHCI_PS_WKOC_E		0x00400000	/* RW wake on over current ena */
142 #define	EHCI_PS_WKDSCNNT_E	0x00200000	/* RW wake on disconnect ena */
143 #define	EHCI_PS_WKCNNT_E	0x00100000	/* RW wake on connect ena */
144 #define	EHCI_PS_PTC		0x000f0000	/* RW port test control */
145 #define	EHCI_PS_PIC		0x0000c000	/* RW port indicator control */
146 #define	EHCI_PS_PO		0x00002000	/* RW port owner */
147 #define	EHCI_PS_PP		0x00001000	/* RW,RO port power */
150 #define	EHCI_PS_PR		0x00000100	/* RW port reset */
151 #define	EHCI_PS_SUSP		0x00000080	/* RW suspend */
152 #define	EHCI_PS_FPR		0x00000040	/* RW force port resume */
156 #define	EHCI_PS_PE		0x00000004	/* RW port enable */
170 #define	EHCI_USBMODE_NOLPM	0x68	/* RW USB Device mode reg (no LPM) */
171 #define	EHCI_USBMODE_LPM	0xC8	/* RW USB Device mode reg (LPM) */
184 #define	EHCI_HOSTC(n)		(0x80+(4*(n)))	/* RO, RW Host mode control reg */