Lines Matching refs:temp
173 uint32_t temp;
176 temp = count & ~3;
179 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
183 count -= temp;
190 if (buf_res.length > temp)
191 buf_res.length = temp;
199 temp -= buf_res.length;
200 } while (temp != 0);
223 uint32_t temp;
226 temp = count & ~3;
229 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
233 count -= temp;
240 if (buf_res.length > temp)
241 buf_res.length = temp;
250 temp -= buf_res.length;
251 } while (temp != 0);
276 uint32_t temp;
282 for (temp = 0; temp != 16; temp++) {
473 uint32_t temp;
476 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK;
477 if (temp >= 10000)
478 temp /= 1000;
480 temp /= 125;
483 if (temp >= 54)
484 temp = 60; /* MHz */
485 else if (temp >= 39)
486 temp = 48; /* MHz */
488 temp = 30; /* MHz */
491 temp *= 125;
493 temp *= 1000;
495 DPRINTF("HFIR=0x%08x\n", temp);
497 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp);
529 uint32_t temp;
537 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
538 temp &= ~DCTL_SFTDISCON;
539 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
546 uint32_t temp;
553 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
554 temp |= DCTL_SFTDISCON;
555 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
629 uint32_t temp;
632 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
633 temp |= DCTL_RMTWKUPSIG;
634 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
639 temp &= ~DCTL_RMTWKUPSIG;
640 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
670 uint32_t temp;
674 temp = DWC_OTG_READ_4(sc, DOTG_DCFG);
675 temp &= ~DCFG_DEVADDR_SET(0x7F);
676 temp |= DCFG_DEVADDR_SET(addr);
677 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp);
717 uint32_t temp;
719 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
727 if (!(temp & GINTSTS_PTXFEMP)) {
736 if (!(temp & GINTSTS_NPTXFEMP)) {
1097 uint32_t temp;
1180 temp = sc->sc_out_ctl[0];
1184 temp | DOEPCTL_STALL);
1186 temp = sc->sc_in_ctl[0];
1190 temp | DIEPCTL_STALL);
1663 uint32_t temp;
1740 temp = sc->sc_out_ctl[td->ep_no];
1743 if ((temp & DIEPCTL_EPTYPE_MASK) ==
1746 if (temp & DIEPCTL_SETD1PID) {
1747 temp &= ~DIEPCTL_SETD1PID;
1748 temp |= DIEPCTL_SETD0PID;
1750 temp &= ~DIEPCTL_SETD0PID;
1751 temp |= DIEPCTL_SETD1PID;
1753 sc->sc_out_ctl[td->ep_no] = temp;
1781 temp = sc->sc_out_ctl[td->ep_no];
1782 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp |
2133 uint32_t temp;
2143 temp = sc->sc_last_rx_status;
2145 if ((td->ep_no == 0) && (temp != 0) &&
2146 (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2147 if ((temp & GRXSTSRD_PKTSTS_MASK) !=
2149 (temp & GRXSTSRD_PKTSTS_MASK) !=
2168 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2171 cpkt = DXEPTSIZ_GET_NPKT(temp);
2217 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2219 if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2222 DXEPTSIZ_GET_NPKT(temp),
2223 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no)));
2279 temp = sc->sc_in_ctl[td->ep_no];
2282 if ((temp & DIEPCTL_EPTYPE_MASK) ==
2285 if (temp & DIEPCTL_SETD1PID) {
2286 temp &= ~DIEPCTL_SETD1PID;
2287 temp |= DIEPCTL_SETD0PID;
2289 temp &= ~DIEPCTL_SETD0PID;
2290 temp |= DIEPCTL_SETD1PID;
2292 sc->sc_in_ctl[td->ep_no] = temp;
2296 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp |
2318 uint32_t temp;
2323 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2326 if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2336 temp = sc->sc_last_rx_status;
2338 if ((td->ep_no == 0) && (temp != 0) &&
2339 (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2340 if ((temp & GRXSTSRD_PKTSTS_MASK) ==
2342 (temp & GRXSTSRD_PKTSTS_MASK) ==
2494 uint16_t temp;
2497 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK;
2499 if (sc->sc_last_frame_num == temp)
2502 sc->sc_last_frame_num = temp;
2506 if ((temp & 7) == 0) {
2535 td->tt_start_slot = temp + slot;
2556 td->tt_start_slot = temp;
2582 td->tt_start_slot = temp;
2602 td->tt_start_slot = temp;
2608 if ((temp & 7) < 6) {
2622 td->tt_start_slot = temp;
2653 if ((temp & 7) == 0) {
2655 (int)temp, (int)sc->sc_needsof);
2681 uint32_t temp;
2707 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
2708 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp);
2709 temp &= ~HCINT_SOFTWARE_ONLY;
2710 sc->sc_chan_state[x].hcint |= temp;
2715 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2716 if (temp & GINTSTS_RXFLVL) {
2725 temp = sc->sc_last_rx_status &
2729 if (temp != GRXSTSRD_STP_DATA &&
2730 temp != GRXSTSRD_STP_COMPLETE &&
2731 temp != GRXSTSRD_OUT_DATA) {
2733 if (temp == GRXSTSRH_HALTED) {
2747 temp = GRXSTSRD_BCNT_GET(
2753 sc->sc_current_rx_bytes = (temp + 3) & ~3;
2756 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no);
2875 uint32_t temp;
2879 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x));
2885 if (temp != 0)
2886 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp);
2938 uint32_t temp;
2958 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
2959 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI)
3065 uint32_t temp;
3067 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
3069 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp);
3072 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
3086 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp)
3091 td = temp->td_next;
3092 temp->td = td;
3095 temp->td_next = td->obj_next;
3098 td->func = temp->func;
3099 td->pc = temp->pc;
3100 td->offset = temp->offset;
3101 td->remainder = temp->len;
3106 td->did_stall = temp->did_stall;
3107 td->short_pkt = temp->short_pkt;
3108 td->alt_next = temp->setup_alt_next;
3124 struct dwc_otg_std_temp temp;
3134 temp.max_frame_size = xfer->max_frame_size;
3140 /* setup temp */
3142 temp.pc = NULL;
3143 temp.td = NULL;
3144 temp.td_next = xfer->td_start[0];
3145 temp.offset = 0;
3146 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
3148 temp.did_stall = !xfer->flags_int.control_stall;
3157 temp.func = &dwc_otg_host_setup_tx;
3159 temp.func = &dwc_otg_setup_rx;
3161 temp.len = xfer->frlengths[0];
3162 temp.pc = xfer->frbuffers + 0;
3163 temp.short_pkt = temp.len ? 1 : 0;
3169 temp.setup_alt_next = 0;
3172 dwc_otg_setup_standard_chain_sub(&temp);
3182 temp.func = &dwc_otg_host_data_rx;
3185 temp.func = &dwc_otg_data_tx;
3190 temp.func = &dwc_otg_host_data_tx;
3193 temp.func = &dwc_otg_data_rx;
3199 temp.pc = xfer->frbuffers + x;
3206 temp.len = xfer->frlengths[x];
3213 temp.setup_alt_next = 0;
3216 temp.setup_alt_next = 0;
3219 if (temp.len == 0) {
3222 temp.short_pkt = 0;
3227 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
3230 dwc_otg_setup_standard_chain_sub(&temp);
3233 temp.offset += temp.len;
3236 temp.pc = xfer->frbuffers + x;
3242 temp.pc = xfer->frbuffers + 0;
3243 temp.len = 0;
3244 temp.short_pkt = 0;
3245 temp.setup_alt_next = 0;
3250 temp.func = &dwc_otg_data_tx_sync;
3251 dwc_otg_setup_standard_chain_sub(&temp);
3262 temp.func = &dwc_otg_host_data_tx;
3265 temp.func = &dwc_otg_data_rx;
3270 temp.func = &dwc_otg_host_data_rx;
3273 temp.func = &dwc_otg_data_tx;
3278 dwc_otg_setup_standard_chain_sub(&temp);
3281 td = temp.td;
3286 temp.func = &dwc_otg_data_tx_sync;
3287 dwc_otg_setup_standard_chain_sub(&temp);
3293 temp.pc = xfer->frbuffers + 0;
3294 temp.len = 0;
3295 temp.short_pkt = 0;
3296 temp.setup_alt_next = 0;
3299 temp.func = &dwc_otg_data_tx_sync;
3300 dwc_otg_setup_standard_chain_sub(&temp);
3305 td = temp.td;
3653 uint32_t temp;
3676 temp = sc->sc_in_ctl[ep_no & UE_ADDR];
3679 temp = sc->sc_out_ctl[ep_no & UE_ADDR];
3683 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3684 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL);
3708 uint32_t temp;
3726 temp = DIEPCTL_EPTYPE_SET(
3730 temp = DIEPCTL_EPTYPE_SET(
3734 temp = DIEPCTL_EPTYPE_SET(
3739 temp |= DIEPCTL_MPS_SET(mps);
3740 temp |= DIEPCTL_TXFNUM_SET(ep_no);
3743 sc->sc_in_ctl[ep_no] = temp;
3745 sc->sc_out_ctl[ep_no] = temp;
3747 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3748 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID);
3749 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK);
3837 uint32_t temp;
3881 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID);
3882 DPRINTF("Version = 0x%08x\n", temp);
3899 temp = GUSBCFG_FORCEDEVMODE;
3902 temp = GUSBCFG_FORCEHOSTMODE;
3905 temp = 0;
3919 GUSBCFG_TRD_TIM_SET(5) | temp);
3923 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3925 temp & ~GLPMCFG_HSIC_CONN);
3927 temp | GLPMCFG_HSIC_CONN);
3932 GUSBCFG_TRD_TIM_SET(5) | temp);
3935 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3937 temp & ~GLPMCFG_HSIC_CONN);
3942 GUSBCFG_TRD_TIM_SET(5) | temp);
3945 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3947 temp & ~GLPMCFG_HSIC_CONN);
3952 GUSBCFG_TRD_TIM_SET(5) | temp);
3955 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3957 temp & ~GLPMCFG_HSIC_CONN);
3959 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO);
3960 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN);
3961 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN |
3963 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp);
3986 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3);
3988 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp);
3990 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
3992 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp);
3997 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp);
4002 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4);
4004 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp);
4022 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
4023 if (temp & GHWCFG2_MPI) {
4042 temp = DWC_OTG_READ_4(sc, DOTG_HCFG);
4043 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK);
4044 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT);
4045 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp);
4057 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
4059 DPRINTFN(5, "GOTCTL=0x%08x\n", temp);
4062 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
4189 uint32_t temp;
4196 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM);
4199 framenum = (temp & HFNUM_FRNUM_MASK);
4201 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
4204 framenum = DSTS_SOFFN_GET(temp);