Lines Matching +full:hsic +full:- +full:state
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved.
6 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved.
43 * NOTE: Writing to non-existing registers appears to cause an
95 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
111 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2/3 - ULPI/HSIC/INTERNAL/UTMI+");
161 sc = DWC_OTG_BUS2SC(udev->bus);
163 if (ep_addr < sc->sc_dev_ep_max)
164 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb;
175 /* round down length to nearest 4-bytes */
182 /* pre-subtract length */
183 count -= temp;
194 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
199 temp -= buf_res.length;
206 sc->sc_bounce_buffer[(count - 1) / 4] = 0;
210 sc->sc_bounce_buffer, count);
213 bus_space_write_region_4(sc->sc_io_tag,
214 sc->sc_io_hdl, fifo, sc->sc_bounce_buffer,
225 /* round down length to nearest 4-bytes */
232 /* pre-subtract length */
233 count -= temp;
244 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
245 sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4);
248 sc->sc_current_rx_fifo += buf_res.length;
249 sc->sc_current_rx_bytes -= buf_res.length;
250 temp -= buf_res.length;
257 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
258 sc->sc_current_rx_fifo,
259 sc->sc_bounce_buffer, (count + 3) / 4);
262 usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count);
268 sc->sc_current_rx_bytes -= count;
269 sc->sc_current_rx_fifo += count;
298 fifo_size = sc->sc_fifo_size;
312 fifo_size -= fifo_regs;
326 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n");
332 sc->sc_active_rx_ep = 0;
334 /* split equally for periodic and non-periodic */
348 for (x = 0; x != sc->sc_host_ch_max; x++) {
358 /* reset host channel state */
359 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
363 (1U << sc->sc_host_ch_max) - 1U);
366 sc->sc_irq_mask |= GINTMSK_HCHINTMSK;
367 sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK;
368 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
374 fifo_size -= 0x40;
378 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0];
381 sc->sc_active_rx_ep = 1;
383 for (x = 1; x != sc->sc_dev_ep_max; x++) {
384 pf = sc->sc_hw_ep_profile + x;
386 pf->usb.max_out_frame_size = 1024 * 3;
387 pf->usb.is_simplex = 0; /* assume duplex */
388 pf->usb.support_bulk = 1;
389 pf->usb.support_interrupt = 1;
390 pf->usb.support_isochronous = 1;
391 pf->usb.support_out = 1;
393 if (x < sc->sc_dev_in_ep_max) {
402 pf->max_buffer = limit;
403 pf->usb.support_in = 1;
407 pf->usb.support_in = 1;
409 pf->usb.is_simplex = 1;
417 fifo_size -= limit;
418 pf->usb.max_in_frame_size = limit;
420 pf->usb.is_simplex = 1;
424 pf->usb.max_in_frame_size,
425 pf->usb.max_out_frame_size);
429 sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK;
430 sc->sc_irq_mask |= GINTMSK_IEPINTMSK;
431 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
444 sc->sc_active_rx_ep = 0;
446 /* reset host channel state */
447 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
459 return (udev->speed != USB_SPEED_HIGH &&
460 udev->parent_hs_hub != NULL &&
461 udev->parent_hs_hub->parent_hub != NULL);
482 /* figure out nearest X-tal value */
490 if (sc->sc_flags.status_high_speed)
504 if (sc->sc_flags.clocks_off &&
505 sc->sc_flags.port_powered) {
508 /* TODO - platform specific */
510 sc->sc_flags.clocks_off = 0;
517 if (!sc->sc_flags.clocks_off) {
520 /* TODO - platform specific */
522 sc->sc_flags.clocks_off = 1;
533 if (!sc->sc_flags.d_pulled_up &&
534 sc->sc_flags.port_powered) {
535 sc->sc_flags.d_pulled_up = 1;
550 if (sc->sc_flags.d_pulled_up) {
551 sc->sc_flags.d_pulled_up = 0;
563 if (sc->sc_flags.status_device_mode != 0)
566 sc->sc_needsof = 1;
568 if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0)
570 sc->sc_irq_mask |= GINTMSK_SOFMSK;
571 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
577 if (sc->sc_flags.status_suspend) {
579 sc->sc_flags.status_suspend = 0;
580 sc->sc_flags.change_suspend = 1;
582 if (sc->sc_flags.status_device_mode) {
587 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK;
588 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
589 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
600 if (!sc->sc_flags.status_suspend) {
602 sc->sc_flags.status_suspend = 1;
603 sc->sc_flags.change_suspend = 1;
605 if (sc->sc_flags.status_device_mode) {
610 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK;
611 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK;
612 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
623 if (!sc->sc_flags.status_suspend)
628 if (sc->sc_flags.status_device_mode) {
637 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
646 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
649 sc->sc_hprt_val |= HPRT_PRTRES;
650 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
653 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
656 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES);
657 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
660 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
686 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK;
687 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
689 if (sc->sc_current_rx_bytes != 0) {
691 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
692 sc->sc_current_rx_fifo, sc->sc_bounce_buffer,
693 sc->sc_current_rx_bytes / 4);
695 sc->sc_current_rx_bytes = 0;
698 sc->sc_last_rx_status = 0;
711 sc->sc_chan_state[x].hcint = 0;
721 if (td->ep_type == UE_ISOCHRONOUS) {
729 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) {
730 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK;
731 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
737 DPRINTF("Non-periodic TX FIFO is not empty\n");
738 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) {
739 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK;
740 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
756 if (td->channel[0] < DWC_OTG_MAX_CHANNELS)
760 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
761 return (1); /* busy - cannot transfer data */
766 return (1); /* busy - cannot transfer data */
768 z = td->max_packet_count;
769 for (x = y = 0; x != sc->sc_host_ch_max; x++) {
771 if (sc->sc_chan_state[x].allocated != 0)
774 if (sc->sc_chan_state[x].wait_halted != 0)
777 td->channel[y++] = x;
784 td->channel[0] = DWC_OTG_MAX_CHANNELS;
785 td->channel[1] = DWC_OTG_MAX_CHANNELS;
786 td->channel[2] = DWC_OTG_MAX_CHANNELS;
789 return (1); /* busy - not enough channels */
793 x = td->channel[y];
796 sc->sc_chan_state[x].allocated = 1;
799 sc->sc_chan_state[x].wait_halted = 1;
805 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt);
808 sc->sc_active_rx_ep |= (1 << x);
819 if (td->channel[index] >= DWC_OTG_MAX_CHANNELS)
823 x = td->channel[index];
824 td->channel[index] = DWC_OTG_MAX_CHANNELS;
832 sc->sc_chan_state[x].allocated = 0;
835 if (sc->sc_last_rx_status != 0 &&
836 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) {
841 sc->sc_active_rx_ep &= ~(1 << x);
844 if (sc->sc_chan_state[x].wait_halted == 0)
855 sc->sc_chan_state[x].wait_halted = 0;
863 for (x = 0; x != td->max_packet_count; x++)
872 if (sc->sc_last_rx_status == 0)
874 for (x = 0; x != td->max_packet_count; x++) {
875 if (td->channel[x] >= DWC_OTG_MAX_CHANNELS ||
876 td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status))
893 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) {
894 hcint = sc->sc_chan_state[td->channel[0]].hcint;
897 td->channel[0], td->state, hcint,
898 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])),
899 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0])));
909 DPRINTF("CH=%d STALL\n", td->channel[0]);
910 td->error_stall = 1;
911 td->error_any = 1;
914 DPRINTF("CH=%d ERROR\n", td->channel[0]);
915 td->errcnt++;
916 if (td->hcsplt != 0 || td->errcnt >= 3) {
917 td->error_any = 1;
925 td->errcnt = 0;
929 switch (td->state) {
935 td->did_nak = 1;
936 td->tt_scheduled = 0;
939 td->offset += td->tx_bytes;
940 td->remainder -= td->tx_bytes;
941 td->toggle = 1;
942 td->tt_scheduled = 0;
949 td->did_nak = 1;
950 td->tt_scheduled = 0;
961 td->did_nak = 1;
962 td->tt_scheduled = 0;
965 td->offset += td->tx_bytes;
966 td->remainder -= td->tx_bytes;
967 td->toggle = 1;
984 if (sizeof(req) != td->remainder) {
985 td->error_any = 1;
989 if (td->hcsplt != 0) {
990 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
991 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
992 td->state = DWC_CHAN_ST_START;
995 delta = sc->sc_last_frame_num - td->tt_start_slot;
998 td->tt_scheduled = 0;
999 td->state = DWC_CHAN_ST_START;
1006 td->state = DWC_CHAN_ST_START;
1010 if (td->hcsplt != 0) {
1011 td->hcsplt &= ~HCSPLT_COMPSPLT;
1012 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1014 td->state = DWC_CHAN_ST_WAIT_ANE;
1018 usbd_copy_out(td->pc, 0, &req, sizeof(req));
1020 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1025 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1027 hcchar = td->hcchar;
1032 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1035 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
1036 DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4);
1039 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1042 td->tx_bytes = sizeof(req);
1049 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1050 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1051 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1054 delta = sc->sc_last_frame_num - td->tt_start_slot;
1057 if (td->ep_type != UE_ISOCHRONOUS)
1058 td->error_any = 1;
1063 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1068 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1070 td->hcsplt |= HCSPLT_COMPSPLT;
1071 td->state = DWC_CHAN_ST_WAIT_C_ANE;
1073 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1076 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1078 hcchar = td->hcchar;
1083 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1102 if (sc->sc_last_rx_status == 0)
1105 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0)
1108 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1110 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1111 GRXSTSRD_STP_COMPLETE || td->remainder != 0) {
1121 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
1128 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status);
1131 td->did_stall = 0;
1134 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1145 dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req));
1148 usbd_copy_out(td->pc, 0, &req, sizeof(req));
1150 td->offset = sizeof(req);
1151 td->remainder = 0;
1171 td->did_stall = 1;
1175 if (!td->did_stall) {
1176 td->did_stall = 1;
1180 temp = sc->sc_out_ctl[0];
1186 temp = sc->sc_in_ctl[0];
1200 delta = sc->sc_tmr_val - td->tmr_val;
1204 td->tmr_val = sc->sc_tmr_val + td->tmr_res;
1207 if (td->set_toggle) {
1208 td->set_toggle = 0;
1209 td->toggle = 1;
1217 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num;
1219 if (td->ep_type == UE_ISOCHRONOUS) {
1221 if (frame_num & (td->tmr_res - 1))
1223 if ((frame_num ^ td->tmr_val) & td->tmr_res)
1225 td->tmr_val = td->tmr_res + sc->sc_last_frame_num;
1226 td->toggle = 0;
1228 } else if (td->ep_type == UE_INTERRUPT) {
1229 if (!td->tt_scheduled)
1231 td->tt_scheduled = 0;
1233 } else if (td->did_nak != 0) {
1235 if (td->tmr_res == frame_num) {
1240 } else if (td->set_toggle) {
1241 td->set_toggle = 0;
1242 td->toggle = 1;
1245 td->tmr_res = frame_num;
1246 td->did_nak = 0;
1259 if (sc->sc_last_rx_status == 0)
1265 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel)
1268 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) {
1272 (int)td->state, (int)sc->sc_last_rx_status);
1274 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) {
1284 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1287 if (td->ep_type == UE_ISOCHRONOUS) {
1288 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
1291 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE;
1294 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
1296 if (count != td->remainder) {
1298 td->short_pkt = 1;
1299 td->got_short = 1;
1304 if (count != td->max_packet_size) {
1305 if (count < td->max_packet_size) {
1307 td->short_pkt = 1;
1308 td->got_short = 1;
1311 td->error_any = 1;
1318 td->toggle ^= 1;
1319 td->tt_scheduled = 0;
1323 if (count > td->remainder) {
1325 td->error_any = 1;
1333 dwc_otg_read_fifo(sc, td->pc, td->offset, count);
1335 td->remainder -= count;
1336 td->offset += count;
1337 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY;
1359 for (x = 0; x != td->max_packet_count; x++) {
1360 channel = td->channel[x];
1363 hcint |= sc->sc_chan_state[channel].hcint;
1366 channel, td->state, hcint,
1376 td->error_stall = 1;
1377 td->error_any = 1;
1381 td->errcnt++;
1382 if (td->hcsplt != 0 || td->errcnt >= 3) {
1383 if (td->ep_type != UE_ISOCHRONOUS) {
1384 td->error_any = 1;
1395 hcint |= sc->sc_chan_state[channel].hcint;
1400 td->errcnt = 0;
1404 switch (td->state) {
1406 if (td->hcsplt != 0)
1413 if (td->ep_type == UE_INTERRUPT) {
1425 td->toggle ^= 1;
1428 } else if (td->ep_type == UE_ISOCHRONOUS) {
1429 if (td->hcsplt != 0) {
1444 td->did_nak = 1;
1445 td->tt_scheduled = 0;
1446 if (td->hcsplt != 0)
1451 if (td->hcsplt != 0) {
1456 td->error_any = 1;
1460 /* wait for data - ACK arrived first */
1464 if (td->ep_type == UE_ISOCHRONOUS) {
1466 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) {
1468 } else if (td->hcsplt != 0) {
1476 if ((td->remainder == 0) || (td->got_short != 0)) {
1477 if (td->short_pkt)
1485 td->tt_scheduled = 0;
1486 td->did_nak = 0;
1487 if (td->hcsplt != 0)
1501 td->did_nak = 1;
1502 td->tt_scheduled = 0;
1505 td->tt_scheduled = 0;
1508 td->did_nak = 0;
1525 if (td->hcsplt != 0) {
1526 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1527 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1528 if (td->ep_type != UE_ISOCHRONOUS) {
1529 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1533 delta = sc->sc_last_frame_num - td->tt_start_slot;
1535 if (td->ep_type != UE_ISOCHRONOUS) {
1537 td->error_any = 1;
1542 td->hcsplt |= HCSPLT_COMPSPLT;
1544 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1550 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1555 if (td->set_toggle) {
1556 td->set_toggle = 0;
1557 td->toggle = 1;
1560 td->state = DWC_CHAN_ST_WAIT_ANE;
1562 for (x = 0; x != td->max_packet_count; x++) {
1563 channel = td->channel[x];
1567 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) |
1569 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
1572 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1574 hcchar = td->hcchar;
1577 if (td->ep_type == UE_ISOCHRONOUS) {
1578 if (td->hcsplt != 0) {
1580 if (sc->sc_last_frame_num & 1)
1586 if (sc->sc_last_frame_num & 1)
1599 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1607 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1608 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1609 td->state = DWC_CHAN_ST_START;
1612 delta = sc->sc_last_frame_num - td->tt_start_slot;
1615 td->tt_scheduled = 0;
1616 td->state = DWC_CHAN_ST_START;
1622 td->state = DWC_CHAN_ST_START;
1626 channel = td->channel[0];
1628 td->hcsplt &= ~HCSPLT_COMPSPLT;
1629 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1635 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1638 if ((sc->sc_last_frame_num & 1) == 0 &&
1639 td->ep_type == UE_ISOCHRONOUS)
1640 td->hcchar |= HCCHAR_ODDFRM;
1642 td->hcchar &= ~HCCHAR_ODDFRM;
1644 hcchar = td->hcchar;
1648 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1670 if (sc->sc_last_rx_status == 0)
1673 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no)
1677 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1679 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1681 if (td->remainder == 0) {
1692 td->error_any = 1;
1696 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1704 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1707 if (count != td->max_packet_size) {
1708 if (count < td->max_packet_size) {
1710 td->short_pkt = 1;
1714 td->error_any = 1;
1722 if (count > td->remainder) {
1724 td->error_any = 1;
1732 dwc_otg_read_fifo(sc, td->pc, td->offset, count);
1734 td->remainder -= count;
1735 td->offset += count;
1740 temp = sc->sc_out_ctl[td->ep_no];
1753 sc->sc_out_ctl[td->ep_no] = temp;
1757 if ((td->remainder == 0) || got_short) {
1758 if (td->short_pkt) {
1768 if (td->ep_no == 0) {
1772 DXEPTSIZ_SET_NBYTES(td->max_packet_size));
1775 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no),
1779 ((td->max_packet_size + 3) & ~3)));
1781 temp = sc->sc_out_ctl[td->ep_no];
1782 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp |
1801 channel = td->channel[td->npkt];
1804 hcint = sc->sc_chan_state[channel].hcint;
1807 channel, td->state, hcint,
1816 td->error_stall = 1;
1817 td->error_any = 1;
1821 td->errcnt++;
1822 if (td->hcsplt != 0 || td->errcnt >= 3) {
1823 td->error_any = 1;
1831 td->errcnt = 0;
1837 switch (td->state) {
1843 td->did_nak = 1;
1844 td->tt_scheduled = 0;
1847 td->offset += td->tx_bytes;
1848 td->remainder -= td->tx_bytes;
1849 td->toggle ^= 1;
1852 td->did_nak = 1;
1854 td->did_nak = 0;
1855 td->tt_scheduled = 0;
1858 if (td->remainder == 0) {
1859 if (td->short_pkt)
1873 td->did_nak = 1;
1874 td->tt_scheduled = 0;
1877 td->did_nak = 0;
1886 td->did_nak = 1;
1887 td->tt_scheduled = 0;
1890 td->offset += td->tx_bytes;
1891 td->remainder -= td->tx_bytes;
1892 td->toggle ^= 1;
1893 td->did_nak = 0;
1894 td->tt_scheduled = 0;
1897 if (td->remainder == 0) {
1898 if (td->short_pkt)
1915 td->offset += td->tx_bytes;
1916 td->remainder -= td->tx_bytes;
1927 if (td->hcsplt != 0) {
1928 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1929 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1930 td->state = DWC_CHAN_ST_START;
1933 delta = sc->sc_last_frame_num - td->tt_start_slot;
1936 td->tt_scheduled = 0;
1937 td->state = DWC_CHAN_ST_START;
1941 td->state = DWC_CHAN_ST_START;
1947 td->state = DWC_CHAN_ST_START;
1952 if (td->set_toggle) {
1953 td->set_toggle = 0;
1954 td->toggle = 1;
1957 if (td->ep_type == UE_ISOCHRONOUS) {
1959 td->state = DWC_CHAN_ST_TX_WAIT_ISOC;
1960 td->hcsplt &= ~HCSPLT_COMPSPLT;
1961 if (td->hcsplt != 0) {
1963 count = td->remainder;
1966 td->error_any = 1;
1970 td->hcsplt &= ~HCSPLT_XACTPOS_MASK;
1971 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT);
1973 } else if (td->hcsplt != 0) {
1974 td->hcsplt &= ~HCSPLT_COMPSPLT;
1976 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1979 td->state = DWC_CHAN_ST_WAIT_ANE;
1982 td->tx_bytes = 0;
1984 for (x = 0; x != td->max_packet_count; x++) {
1987 channel = td->channel[x];
1990 count = td->max_packet_size;
1991 rem_bytes = td->remainder - td->tx_bytes;
1994 td->short_pkt = 1;
2004 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
2020 } else if (td->ep_type == UE_ISOCHRONOUS &&
2021 td->max_packet_count > 1) {
2033 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
2037 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2039 hcchar = td->hcchar;
2043 if ((sc->sc_last_frame_num & 1) == 0 &&
2044 td->ep_type == UE_ISOCHRONOUS)
2054 dwc_otg_write_fifo(sc, td->pc, td->offset +
2055 td->tx_bytes, DOTG_DFIFO(channel), count);
2059 td->tx_bytes += count;
2062 td->npkt = x;
2074 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
2075 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
2076 td->state = DWC_CHAN_ST_WAIT_C_PKT;
2079 delta = sc->sc_last_frame_num - td->tt_start_slot;
2082 if (td->ep_type != UE_ISOCHRONOUS)
2083 td->error_any = 1;
2089 td->state = DWC_CHAN_ST_WAIT_C_PKT;
2093 channel = td->channel[0];
2095 td->hcsplt |= HCSPLT_COMPSPLT;
2096 td->state = DWC_CHAN_ST_WAIT_C_ANE;
2101 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2103 hcchar = td->hcchar;
2107 if ((sc->sc_last_frame_num & 1) != 0 &&
2108 td->ep_type == UE_ISOCHRONOUS)
2117 td->tt_complete_slot = sc->sc_last_frame_num + 1;
2138 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer;
2143 temp = sc->sc_last_rx_status;
2145 if ((td->ep_no == 0) && (temp != 0) &&
2151 /* dump data - wrong direction */
2158 td->error_any = 1;
2164 if (td->tx_bytes != 0) {
2168 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2173 if (cpkt >= td->npkt) {
2177 fifo_left = (td->npkt - cpkt) *
2178 td->max_packet_size;
2183 fifo_left = td->max_packet_size;
2187 count = td->tx_bytes;
2193 dwc_otg_write_fifo(sc, td->pc, td->offset,
2194 DOTG_DFIFO(td->ep_no), count);
2196 td->tx_bytes -= count;
2197 td->remainder -= count;
2198 td->offset += count;
2199 td->npkt = cpkt;
2201 if (td->tx_bytes != 0)
2205 if (td->remainder == 0) {
2206 if (td->short_pkt)
2213 if (!to--)
2217 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2221 "DIEPCTL=0x%08x\n", td->ep_no,
2223 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no)));
2228 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no);
2231 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) {
2233 mpkt = max_buffer / td->max_packet_size;
2238 count = td->remainder;
2240 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size);
2242 td->npkt = count / td->max_packet_size;
2247 * have a dependency towards non-generic chip features
2248 * to disable the TX-FIFO-EMPTY interrupts on a per
2252 if (td->npkt > mpkt) {
2253 td->npkt = mpkt;
2254 count = td->max_packet_size * mpkt;
2255 } else if ((count == 0) || (count % td->max_packet_size)) {
2257 td->npkt++;
2258 td->short_pkt = 1;
2263 count = td->max_packet_size;
2264 if (td->remainder < count) {
2266 td->short_pkt = 1;
2267 count = td->remainder;
2269 td->npkt = 1;
2271 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no),
2273 DXEPTSIZ_SET_NPKT(td->npkt) |
2277 td->npkt += mpkt;
2279 temp = sc->sc_in_ctl[td->ep_no];
2292 sc->sc_in_ctl[td->ep_no] = temp;
2296 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp |
2299 td->tx_bytes = count;
2302 if (td->tx_bytes == 0 &&
2303 td->remainder == 0) {
2304 if (td->short_pkt)
2323 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2327 DPRINTFN(5, "busy ep=%d\n", td->ep_no);
2336 temp = sc->sc_last_rx_status;
2338 if ((td->ep_no == 0) && (temp != 0) &&
2350 /* dump data - wrong direction */
2367 td = xfer->td_transfer_cache;
2372 if ((td->func) (sc, td)) {
2376 if (((void *)td) == xfer->td_transfer_last) {
2379 if (td->error_any) {
2381 } else if (td->remainder > 0) {
2386 if (!td->alt_next)
2394 tmr_res = td->tmr_res;
2395 tmr_val = td->tmr_val;
2396 toggle = td->toggle;
2397 td = td->obj_next;
2398 xfer->td_transfer_cache = td;
2399 td->toggle = toggle; /* transfer toggle */
2400 td->tmr_res = tmr_res;
2401 td->tmr_val = tmr_val;
2406 xfer->td_transfer_cache = NULL;
2407 sc->sc_xfer_complete = 1;
2417 td = xfer->td_transfer_cache;
2431 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2435 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2438 sc->sc_tmr_val++;
2443 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2445 if (sc->sc_timer_active) {
2447 usb_callout_reset(&sc->sc_timer,
2456 if (sc->sc_timer_active != 0)
2459 sc->sc_timer_active = 1;
2462 usb_callout_reset(&sc->sc_timer,
2470 if (sc->sc_timer_active == 0)
2473 sc->sc_timer_active = 0;
2476 usb_callout_stop(&sc->sc_timer);
2482 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX)
2483 pinfo->slot_index++;
2484 return (pinfo->slot_index);
2499 if (sc->sc_last_frame_num == temp)
2502 sc->sc_last_frame_num = temp;
2508 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info));
2510 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2511 td = xfer->td_transfer_cache;
2512 if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2516 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0)
2519 sc->sc_needsof = 1;
2521 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2526 sc->sc_tt_info + td->tt_index);
2535 td->tt_start_slot = temp + slot;
2536 td->tt_scheduled = 1;
2537 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2541 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2542 td = xfer->td_transfer_cache;
2543 if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2547 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0)
2550 sc->sc_needsof = 1;
2552 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2556 td->tt_start_slot = temp;
2557 td->tt_scheduled = 1;
2558 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2562 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2563 td = xfer->td_transfer_cache;
2564 if (td == NULL || td->ep_type != UE_INTERRUPT)
2567 if (td->tt_scheduled != 0) {
2568 sc->sc_needsof = 1;
2575 if (td->hcsplt == 0) {
2576 sc->sc_needsof = 1;
2577 td->tt_scheduled = 1;
2582 td->tt_start_slot = temp;
2583 sc->sc_needsof = 1;
2584 td->tt_scheduled = 1;
2585 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2589 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2590 td = xfer->td_transfer_cache;
2592 td->ep_type != UE_CONTROL) {
2596 sc->sc_needsof = 1;
2598 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2602 td->tt_start_slot = temp;
2603 td->tt_scheduled = 1;
2604 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2609 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2610 td = xfer->td_transfer_cache;
2612 td->ep_type != UE_BULK) {
2616 sc->sc_needsof = 1;
2618 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2622 td->tt_start_slot = temp;
2623 td->tt_scheduled = 1;
2624 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2630 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2633 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2634 td = xfer->td_transfer_cache;
2635 if (td == NULL || td->hcsplt == 0)
2637 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2640 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry);
2641 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2643 /* put non-TT non-ISOCHRONOUS transfers last */
2644 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2645 td = xfer->td_transfer_cache;
2646 if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS)
2648 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2651 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2655 (int)temp, (int)sc->sc_needsof);
2658 if (sc->sc_irq_mask & GINTMSK_SOFMSK) {
2659 if (sc->sc_needsof == 0) {
2660 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2661 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2664 if (sc->sc_needsof != 0) {
2665 sc->sc_irq_mask |= GINTMSK_SOFMSK;
2666 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2671 sc->sc_needsof = 0;
2686 if (sc->sc_flags.status_device_mode == 0) {
2704 x = ffs(haint) - 1;
2705 if (x >= sc->sc_host_ch_max)
2710 sc->sc_chan_state[x].hcint |= temp;
2714 if (sc->sc_last_rx_status == 0) {
2718 sc->sc_last_rx_status =
2722 if (sc->sc_last_rx_status != 0) {
2725 temp = sc->sc_last_rx_status &
2728 /* non-data messages we simply skip */
2734 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status);
2735 sc->sc_chan_state[ep_no].wait_halted = 0;
2739 sc->sc_current_rx_bytes = 0;
2740 sc->sc_current_rx_fifo = 0;
2748 sc->sc_last_rx_status);
2750 sc->sc_last_rx_status);
2753 sc->sc_current_rx_bytes = (temp + 3) & ~3;
2754 sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no);
2759 if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2767 sc->sc_last_rx_status, ep_no,
2768 (sc->sc_last_rx_status >> 15) & 3,
2769 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status),
2770 (sc->sc_last_rx_status >> 17) & 15);
2778 sc->sc_last_rx_status);
2781 if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2790 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
2795 if (sc->sc_last_rx_status == 0)
2799 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK;
2800 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2810 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2825 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) {
2826 if (!sc->sc_flags.status_vbus) {
2827 sc->sc_flags.status_vbus = 1;
2834 if (sc->sc_flags.status_vbus) {
2835 sc->sc_flags.status_vbus = 0;
2836 sc->sc_flags.status_bus_reset = 0;
2837 sc->sc_flags.status_suspend = 0;
2838 sc->sc_flags.change_suspend = 0;
2839 sc->sc_flags.change_connect = 1;
2855 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2863 /* check for USB state change interrupts */
2868 if (status & sc->sc_irq_mask &
2870 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
2871 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2878 for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
2893 if (sc->sc_xfer_complete != 0)
2896 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2907 USB_BUS_LOCK(&sc->sc_bus);
2908 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2921 /* set correct state */
2922 sc->sc_flags.status_device_mode = 1;
2923 sc->sc_flags.status_bus_reset = 0;
2924 sc->sc_flags.status_suspend = 0;
2925 sc->sc_flags.change_suspend = 0;
2926 sc->sc_flags.change_connect = 1;
2929 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2930 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2936 /* check for any bus state change interrupts */
2942 /* set correct state */
2943 sc->sc_flags.status_device_mode = 1;
2944 sc->sc_flags.status_bus_reset = 1;
2945 sc->sc_flags.status_suspend = 0;
2946 sc->sc_flags.change_suspend = 0;
2947 sc->sc_flags.change_connect = 1;
2948 sc->sc_flags.status_low_speed = 0;
2949 sc->sc_flags.port_enabled = 1;
2960 sc->sc_flags.status_high_speed = 1;
2962 sc->sc_flags.status_high_speed = 0;
2968 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK);
2969 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
2970 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2985 sc->sc_hprt_val);
2989 sc->sc_flags.status_device_mode = 0;
2992 sc->sc_flags.status_bus_reset = 1;
2994 sc->sc_flags.status_bus_reset = 0;
2998 sc->sc_flags.change_enabled = 1;
3001 sc->sc_flags.port_enabled = 1;
3003 sc->sc_flags.port_enabled = 0;
3006 sc->sc_flags.change_over_current = 1;
3009 sc->sc_flags.port_over_current = 1;
3011 sc->sc_flags.port_over_current = 0;
3014 sc->sc_flags.port_powered = 1;
3016 sc->sc_flags.port_powered = 0;
3020 sc->sc_flags.status_low_speed = 1;
3022 sc->sc_flags.status_low_speed = 0;
3026 sc->sc_flags.status_high_speed = 1;
3028 sc->sc_flags.status_high_speed = 0;
3031 sc->sc_flags.change_connect = 1;
3075 if (sc->sc_xfer_complete != 0) {
3076 sc->sc_xfer_complete = 0;
3081 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3082 USB_BUS_UNLOCK(&sc->sc_bus);
3091 td = temp->td_next;
3092 temp->td = td;
3095 temp->td_next = td->obj_next;
3098 td->func = temp->func;
3099 td->pc = temp->pc;
3100 td->offset = temp->offset;
3101 td->remainder = temp->len;
3102 td->tx_bytes = 0;
3103 td->error_any = 0;
3104 td->error_stall = 0;
3105 td->npkt = 0;
3106 td->did_stall = temp->did_stall;
3107 td->short_pkt = temp->short_pkt;
3108 td->alt_next = temp->setup_alt_next;
3109 td->set_toggle = 0;
3110 td->got_short = 0;
3111 td->did_nak = 0;
3112 td->channel[0] = DWC_OTG_MAX_CHANNELS;
3113 td->channel[1] = DWC_OTG_MAX_CHANNELS;
3114 td->channel[2] = DWC_OTG_MAX_CHANNELS;
3115 td->state = 0;
3116 td->errcnt = 0;
3117 td->tt_scheduled = 0;
3118 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
3131 xfer->address, UE_GET_ADDR(xfer->endpointno),
3132 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
3134 temp.max_frame_size = xfer->max_frame_size;
3136 td = xfer->td_start[0];
3137 xfer->td_transfer_first = td;
3138 xfer->td_transfer_cache = td;
3144 temp.td_next = xfer->td_start[0];
3146 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
3147 xfer->flags_int.isochronous_xfr;
3148 temp.did_stall = !xfer->flags_int.control_stall;
3150 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
3154 if (xfer->flags_int.control_xfr) {
3155 if (xfer->flags_int.control_hdr) {
3161 temp.len = xfer->frlengths[0];
3162 temp.pc = xfer->frbuffers + 0;
3166 if (xfer->nframes == 1) {
3168 if (xfer->flags_int.control_act)
3179 if (x != xfer->nframes) {
3180 if (xfer->endpointno & UE_DIR_IN) {
3199 temp.pc = xfer->frbuffers + x;
3203 while (x != xfer->nframes) {
3206 temp.len = xfer->frlengths[x];
3210 if (x == xfer->nframes) {
3211 if (xfer->flags_int.control_xfr) {
3212 if (xfer->flags_int.control_act) {
3227 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
3232 if (xfer->flags_int.isochronous_xfr) {
3236 temp.pc = xfer->frbuffers + x;
3240 if (xfer->flags_int.control_xfr) {
3242 temp.pc = xfer->frbuffers + 0;
3255 if (!xfer->flags_int.control_act) {
3260 if (xfer->endpointno & UE_DIR_IN) {
3282 td->set_toggle = 1;
3293 temp.pc = xfer->frbuffers + 0;
3306 xfer->td_transfer_last = td;
3313 sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3316 td = xfer->td_transfer_first;
3317 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
3320 (xfer->address << HCCHAR_DEVADDR_SHIFT) |
3321 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) |
3322 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) |
3333 * speed USB traffic going through a TT. For non-TT
3338 if (td->ep_type == UE_INTERRUPT)
3341 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT);
3343 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
3346 switch (xfer->xroot->udev->speed) {
3352 if (dwc_otg_uses_split(xfer->xroot->udev)) {
3354 (xfer->xroot->udev->hs_port_no <<
3356 (xfer->xroot->udev->hs_hub_addr <<
3361 if (td->ep_type == UE_INTERRUPT) {
3363 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3368 td->tmr_val = sc->sc_tmr_val + ival;
3369 td->tmr_res = ival;
3370 } else if (td->ep_type == UE_ISOCHRONOUS) {
3371 td->tmr_res = 1;
3372 td->tmr_val = sc->sc_last_frame_num;
3373 if (td->hcchar & HCCHAR_EPDIR_IN)
3374 td->tmr_val++;
3376 td->tmr_val = 0;
3377 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3382 if (td->ep_type == UE_INTERRUPT) {
3384 hcchar |= ((xfer->max_packet_count & 3)
3386 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3391 td->tmr_val = sc->sc_tmr_val + ival;
3392 td->tmr_res = ival;
3393 } else if (td->ep_type == UE_ISOCHRONOUS) {
3394 hcchar |= ((xfer->max_packet_count & 3)
3396 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer);
3397 td->tmr_val = sc->sc_last_frame_num;
3398 if (td->hcchar & HCCHAR_EPDIR_IN)
3399 td->tmr_val += td->tmr_res;
3402 td->tmr_val = 0;
3403 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3408 td->tmr_val = 0;
3409 td->tmr_res = 0;
3415 td->hcchar = hcchar;
3416 td->hcsplt = hcsplt;
3418 if (((void *)td) == xfer->td_transfer_last)
3421 td = td->obj_next;
3433 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
3442 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3451 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3453 if (sc->sc_flags.status_device_mode != 0) {
3458 struct dwc_otg_td *td = xfer->td_transfer_cache;
3459 if (td->ep_type == UE_ISOCHRONOUS &&
3460 (td->hcchar & HCCHAR_EPDIR_IN) == 0) {
3473 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3476 if (xfer->timeout != 0) {
3478 &dwc_otg_timeout, xfer->timeout);
3481 if (sc->sc_flags.status_device_mode != 0)
3487 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3495 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3498 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
3500 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3501 sizeof(sc->sc_hub_idata));
3513 td = xfer->td_transfer_cache;
3516 len = td->remainder;
3519 xfer->endpoint->toggle_next = td->toggle;
3521 if (xfer->aframes != xfer->nframes) {
3526 if (len > xfer->frlengths[xfer->aframes]) {
3527 td->error_any = 1;
3529 xfer->frlengths[xfer->aframes] -= len;
3533 if (td->error_any) {
3535 error = (td->error_stall ?
3542 if (xfer->flags_int.short_frames_ok ||
3543 xfer->flags_int.isochronous_xfr) {
3545 if (td->alt_next) {
3546 td = td->obj_next;
3557 td = td->obj_next;
3567 xfer->td_transfer_cache = td;
3578 xfer, xfer->endpoint);
3582 xfer->td_transfer_cache = xfer->td_transfer_first;
3584 if (xfer->flags_int.control_xfr) {
3585 if (xfer->flags_int.control_hdr) {
3588 xfer->aframes = 1;
3590 if (xfer->td_transfer_cache == NULL) {
3594 while (xfer->aframes != xfer->nframes) {
3596 xfer->aframes++;
3598 if (xfer->td_transfer_cache == NULL) {
3603 if (xfer->flags_int.control_xfr &&
3604 !xfer->flags_int.control_act) {
3611 /*------------------------------------------------------------------------*
3616 *------------------------------------------------------------------------*/
3620 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3623 xfer, xfer->endpoint, error);
3625 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3627 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
3632 td = xfer->td_transfer_cache;
3639 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3657 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3660 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3665 sc = DWC_OTG_BUS2SC(udev->bus);
3667 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3670 ep_no = ep->edesc->bEndpointAddress;
3676 temp = sc->sc_in_ctl[ep_no & UE_ADDR];
3679 temp = sc->sc_out_ctl[ep_no & UE_ADDR];
3688 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR));
3690 if (sc->sc_last_rx_status != 0 &&
3692 sc->sc_last_rx_status)) {
3700 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3719 sc->sc_active_rx_ep |= (1U << ep_no);
3743 sc->sc_in_ctl[ep_no] = temp;
3745 sc->sc_out_ctl[ep_no] = temp;
3774 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3777 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3782 sc = DWC_OTG_BUS2SC(udev->bus);
3784 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3787 ed = ep->edesc;
3791 UGETW(ed->wMaxPacketSize),
3792 (ed->bEndpointAddress & UE_ADDR),
3793 (ed->bmAttributes & UE_XFERTYPE),
3794 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3796 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3806 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3812 sc = DWC_OTG_BUS2SC(udev->bus);
3815 if (udev->state == USB_STATE_CONFIGURED ||
3816 udev->state == USB_STATE_ADDRESSED) {
3817 USB_BUS_LOCK(&sc->sc_bus);
3819 for (x = 1; x != sc->sc_dev_ep_max; x++) {
3820 if (x < sc->sc_dev_in_ep_max) {
3830 USB_BUS_UNLOCK(&sc->sc_bus);
3842 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
3843 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
3844 sc->sc_io_size = rman_get_size(sc->sc_io_res);
3847 sc->sc_bus.devices = sc->sc_devices;
3848 sc->sc_bus.devices_max = DWC_OTG_MAX_DEVICES;
3849 sc->sc_bus.dma_bits = 32;
3850 sc->sc_bus.usbrev = USB_REV_2_0;
3851 sc->sc_bus.methods = &dwc_otg_bus_methods;
3854 if (usb_bus_mem_alloc_all(&sc->sc_bus,
3855 USB_GET_DMA_TAG(sc->sc_bus.parent), NULL)) {
3859 sc->sc_bus.bdev = device_add_child(sc->sc_bus.parent, "usbus", DEVICE_UNIT_ANY);
3860 if (sc->sc_bus.bdev == NULL)
3863 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
3865 err = bus_setup_intr(sc->sc_bus.parent, sc->sc_irq_res,
3867 &dwc_otg_interrupt, sc, &sc->sc_intr_hdl);
3869 sc->sc_intr_hdl = NULL;
3873 usb_callout_init_mtx(&sc->sc_timer,
3874 &sc->sc_bus.bus_mtx, 0);
3876 USB_BUS_LOCK(&sc->sc_bus);
3889 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32);
3895 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128);
3897 switch (sc->sc_mode) {
3909 if (sc->sc_phy_type == 0)
3910 sc->sc_phy_type = dwc_otg_phy_type + 1;
3911 if (sc->sc_phy_bits == 0)
3912 sc->sc_phy_bits = 16;
3914 /* select HSIC, ULPI, UTMI+ or internal PHY mode */
3915 switch (sc->sc_phy_type) {
3941 (sc->sc_phy_bits == 16 ? GUSBCFG_PHYIF : 0) |
3978 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3984 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3988 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp);
3992 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp);
3994 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS)
3995 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS;
3997 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp);
3999 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS)
4000 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS;
4004 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp);
4007 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max,
4008 sc->sc_host_ch_max);
4011 if (dwc_otg_init_fifo(sc, sc->sc_mode)) {
4012 USB_BUS_UNLOCK(&sc->sc_bus);
4017 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ;
4018 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
4020 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) {
4028 for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
4040 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) {
4055 /* read initial VBUS state */
4064 USB_BUS_UNLOCK(&sc->sc_bus);
4068 dwc_otg_do_poll(&sc->sc_bus);
4076 USB_BUS_LOCK(&sc->sc_bus);
4088 sc->sc_flags.port_enabled = 0;
4089 sc->sc_flags.port_powered = 0;
4090 sc->sc_flags.status_vbus = 0;
4091 sc->sc_flags.status_bus_reset = 0;
4092 sc->sc_flags.status_suspend = 0;
4093 sc->sc_flags.change_suspend = 0;
4094 sc->sc_flags.change_connect = 1;
4099 USB_BUS_UNLOCK(&sc->sc_bus);
4101 usb_callout_drain(&sc->sc_timer);
4121 USB_BUS_LOCK(&sc->sc_bus);
4122 USB_BUS_SPIN_LOCK(&sc->sc_bus);
4125 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
4126 USB_BUS_UNLOCK(&sc->sc_bus);
4129 /*------------------------------------------------------------------------*
4133 *------------------------------------------------------------------------*/
4166 /*------------------------------------------------------------------------*
4168 *------------------------------------------------------------------------*/
4188 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
4193 xfer, xfer->endpoint->isoc_next, xfer->nframes);
4195 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) {
4210 if (sc->sc_flags.status_high_speed)
4215 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
4232 /*------------------------------------------------------------------------*
4234 *------------------------------------------------------------------------*
4236 *------------------------------------------------------------------------*/
4305 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4312 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
4315 ptr = (const void *)&sc->sc_hub_temp;
4319 value = UGETW(req->wValue);
4320 index = UGETW(req->wIndex);
4324 switch (req->bmRequestType) {
4326 switch (req->bRequest) {
4339 switch (req->bRequest) {
4355 switch (req->bRequest) {
4357 switch (UGETW(req->wValue)) {
4367 switch (UGETW(req->wValue)) {
4384 switch (req->bRequest) {
4393 switch (req->bRequest) {
4405 switch (req->bRequest) {
4426 switch (req->bRequest) {
4438 switch (req->bRequest) {
4454 switch (req->bRequest) {
4465 switch (req->bRequest) {
4523 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
4528 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
4535 sc->sc_rt_addr = value;
4542 sc->sc_conf = value;
4547 sc->sc_hub_temp.wValue[0] = 0;
4555 USETW(sc->sc_hub_temp.wValue, 0);
4577 if (sc->sc_flags.status_device_mode == 0) {
4579 sc->sc_hprt_val | HPRT_PRTENA);
4581 sc->sc_flags.port_enabled = 0;
4585 sc->sc_flags.change_reset = 0;
4589 sc->sc_flags.change_enabled = 0;
4593 sc->sc_flags.change_over_current = 0;
4602 sc->sc_flags.port_powered = 0;
4603 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4604 sc->sc_hprt_val = 0;
4613 sc->sc_flags.change_connect = 0;
4617 sc->sc_flags.change_suspend = 0;
4637 if (sc->sc_flags.status_device_mode == 0) {
4639 sc->sc_hprt_val |= HPRT_PRTSUSP;
4640 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4648 if (sc->sc_flags.status_device_mode == 0) {
4652 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST);
4655 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4657 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4660 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4665 sc->sc_flags.change_reset = 1;
4676 sc->sc_flags.port_powered = 1;
4677 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4678 sc->sc_hprt_val |= HPRT_PRTPWR;
4679 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4681 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) {
4699 if (sc->sc_flags.status_vbus)
4706 if (sc->sc_flags.status_device_mode) {
4714 if (sc->sc_flags.status_high_speed)
4716 else if (sc->sc_flags.status_low_speed)
4719 if (sc->sc_flags.port_powered)
4722 if (sc->sc_flags.port_enabled)
4725 if (sc->sc_flags.port_over_current)
4728 if (sc->sc_flags.status_vbus &&
4729 sc->sc_flags.status_bus_reset)
4732 if (sc->sc_flags.status_suspend)
4735 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4739 if (sc->sc_flags.change_enabled)
4741 if (sc->sc_flags.change_connect)
4743 if (sc->sc_flags.change_suspend)
4745 if (sc->sc_flags.change_reset)
4747 if (sc->sc_flags.change_over_current)
4750 USETW(sc->sc_hub_temp.ps.wPortChange, value);
4751 len = sizeof(sc->sc_hub_temp.ps);
4781 xfer = parm->curr_xfer;
4788 parm->hc_max_packet_size = 0x500;
4789 parm->hc_max_packet_count = 3;
4790 parm->hc_max_frame_size = 3 * 0x500;
4797 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
4800 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
4803 ntd = xfer->nframes + 1 /* SYNC */ ;
4809 if (parm->err)
4817 ep_no = xfer->endpointno & UE_ADDR;
4822 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4825 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4829 parm->err = USB_ERR_INVAL;
4835 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4840 if (parm->buf) {
4841 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4844 if (dwc_otg_uses_split(parm->udev)) {
4845 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT)
4846 td->tt_index = parm->udev->device_index;
4848 td->tt_index = parm->udev->parent_hs_hub->device_index;
4850 td->tt_index = parm->udev->device_index;
4854 td->max_packet_size = xfer->max_packet_size;
4855 td->max_packet_count = xfer->max_packet_count;
4857 if (td->max_packet_count == 0 || td->max_packet_count > 3)
4858 td->max_packet_count = 1;
4859 td->ep_no = ep_no;
4860 td->ep_type = ep_type;
4861 td->obj_next = last_obj;
4865 parm->size[0] += sizeof(*td);
4868 xfer->td_start[0] = last_obj;
4881 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4884 ep, udev->address,
4885 edesc->bEndpointAddress, udev->flags.usb_mode,
4886 sc->sc_rt_addr, udev->device_index);
4888 if (udev->device_index != sc->sc_rt_addr) {
4889 if (udev->flags.usb_mode == USB_MODE_DEVICE) {
4890 if (udev->speed != USB_SPEED_FULL &&
4891 udev->speed != USB_SPEED_HIGH) {
4896 if (udev->speed == USB_SPEED_HIGH &&
4897 (edesc->wMaxPacketSize[1] & 0x18) != 0 &&
4898 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) {
4900 DPRINTFN(-1, "Non-isochronous high bandwidth "
4905 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
4906 ep->methods = &dwc_otg_device_isoc_methods;
4908 ep->methods = &dwc_otg_device_non_isoc_methods;
4913 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4917 switch (state) {
4935 /* DMA delay - wait until any use of memory is finished */
4945 dwc_otg_do_poll(udev->bus);