52 #define	UART_CTRL		0x08		/* Control Register */  macro
175 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_param()
176 	uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST |  in uart_mvebu_param()
214 	uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_param()
228 	uart_setreg(bas, UART_CTRL, uart_getreg(bas, UART_CTRL) &  in uart_mvebu_init()
331 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_attach()
338 	uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_bus_attach()
361 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_flush()
365 		uart_setreg(bas, UART_CTRL, ctrl | CTRL_RX_FIFO_RST);  in uart_mvebu_bus_flush()
370 		uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST);  in uart_mvebu_bus_flush()
381 		uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_bus_flush()
407 		ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_ioctl()
412 		uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_bus_ioctl()
440 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_ipend()
445 		uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_TX_IDLE_INT);  in uart_mvebu_bus_ipend()
556 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_transmit()
557 	uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);  in uart_mvebu_bus_transmit()
569 	uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_IDLE_INT);  in uart_mvebu_bus_transmit()
588 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_grab()
590 	uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);  in uart_mvebu_bus_grab()
604 	ctrl = uart_getreg(bas, UART_CTRL) & ~CTRL_INTR_MASK;  in uart_mvebu_bus_ungrab()
605 	uart_setreg(bas, UART_CTRL, ctrl | msc->intrm);  in uart_mvebu_bus_ungrab()