Lines Matching +full:rx +full:- +full:ctrl

1 /*-
55 #define CTRL_RX_FIFO_RST (1 << 14) /* RX FIFO Reset */
61 #define CTRL_TX_HALF_INT (1 << 8) /* TX Half-Full Interrupt Enable */
62 #define CTRL_RX_HALF_INT (1 << 7) /* RX Half-Full Interrupt Enable */
65 #define CTRL_RX_RDY_INT (1 << 4) /* RX Ready Interrupt Enable */
77 #define STAT_RX_FIFO_EMPT (1 << 12) /* RX FIFO Empty */
80 #define STAT_RX_TOGL (1 << 9) /* RX Toogled */
81 #define STAT_RX_FIFO_FULL (1 << 8) /* RX FIFO Full */
82 #define STAT_RX_FIFO_HALF (1 << 7) /* RX FIFO Half Full */
85 #define STAT_RX_RDY (1 << 4) /* RX Ready */
127 * Low-level UART interface.
170 uint32_t ctrl = 0; in uart_mvebu_param() local
175 ctrl = uart_getreg(bas, UART_CTRL); in uart_mvebu_param()
176 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST | in uart_mvebu_param()
182 ctrl |= CTRL_TWO_STOP; in uart_mvebu_param()
186 ctrl &=~ CTRL_TWO_STOP; in uart_mvebu_param()
191 ctrl |= CTRL_PAR_EN; in uart_mvebu_param()
194 ctrl &=~ CTRL_PAR_EN; in uart_mvebu_param()
199 divisor = uart_mvebu_divisor(bas->rclk, baudrate); in uart_mvebu_param()
212 ctrl |= CTRL_ST_MIRR_EN; in uart_mvebu_param()
214 uart_setreg(bas, UART_CTRL, ctrl); in uart_mvebu_param()
225 bas->rclk = DEFAULT_RCLK; in uart_mvebu_init()
306 "mvebu-uart",
317 {"marvell,armada-3700-uart", (uintptr_t)&uart_mvebu_class},
326 int ctrl; in uart_mvebu_bus_attach() local
328 bas = &sc->sc_bas; in uart_mvebu_bus_attach()
329 uart_lock(sc->sc_hwmtx); in uart_mvebu_bus_attach()
331 ctrl = uart_getreg(bas, UART_CTRL); in uart_mvebu_bus_attach()
334 ctrl &=~ CTRL_INTR_MASK; in uart_mvebu_bus_attach()
335 ctrl |= CTRL_IPEND_MASK; in uart_mvebu_bus_attach()
338 uart_setreg(bas, UART_CTRL, ctrl); in uart_mvebu_bus_attach()
341 uart_unlock(sc->sc_hwmtx); in uart_mvebu_bus_attach()
357 int ctrl, ret = 0; in uart_mvebu_bus_flush() local
359 bas = &sc->sc_bas; in uart_mvebu_bus_flush()
360 uart_lock(sc->sc_hwmtx); in uart_mvebu_bus_flush()
361 ctrl = uart_getreg(bas, UART_CTRL); in uart_mvebu_bus_flush()
365 uart_setreg(bas, UART_CTRL, ctrl | CTRL_RX_FIFO_RST); in uart_mvebu_bus_flush()
370 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST); in uart_mvebu_bus_flush()
381 uart_setreg(bas, UART_CTRL, ctrl); in uart_mvebu_bus_flush()
385 uart_unlock(sc->sc_hwmtx); in uart_mvebu_bus_flush()
400 int ctrl, ret = 0; in uart_mvebu_bus_ioctl() local
403 bas = &sc->sc_bas; in uart_mvebu_bus_ioctl()
404 uart_lock(sc->sc_hwmtx); in uart_mvebu_bus_ioctl()
407 ctrl = uart_getreg(bas, UART_CTRL); in uart_mvebu_bus_ioctl()
409 ctrl |= CTRL_SND_BRK_SEQ; in uart_mvebu_bus_ioctl()
411 ctrl &=~ CTRL_SND_BRK_SEQ; in uart_mvebu_bus_ioctl()
412 uart_setreg(bas, UART_CTRL, ctrl); in uart_mvebu_bus_ioctl()
418 baudrate = bas->rclk/(divisor * 16); in uart_mvebu_bus_ioctl()
426 uart_unlock(sc->sc_hwmtx); in uart_mvebu_bus_ioctl()
435 int ipend, ctrl, ret = 0; in uart_mvebu_bus_ipend() local
437 bas = &sc->sc_bas; in uart_mvebu_bus_ipend()
438 uart_lock(sc->sc_hwmtx); in uart_mvebu_bus_ipend()
440 ctrl = uart_getreg(bas, UART_CTRL); in uart_mvebu_bus_ipend()
443 (ctrl & CTRL_TX_IDLE_INT) == CTRL_TX_IDLE_INT) { in uart_mvebu_bus_ipend()
445 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_TX_IDLE_INT); in uart_mvebu_bus_ipend()
457 uart_unlock(sc->sc_hwmtx); in uart_mvebu_bus_ipend()
468 uart_lock(sc->sc_hwmtx); in uart_mvebu_bus_param()
469 ret = uart_mvebu_param(&sc->sc_bas, baudrate, databits, stopbits, parity); in uart_mvebu_bus_param()
470 uart_unlock(sc->sc_hwmtx); in uart_mvebu_bus_param()
478 if (!ofw_bus_status_okay(sc->sc_dev)) in uart_mvebu_bus_probe()
481 if (!ofw_bus_search_compatible(sc->sc_dev, compat_data)->ocd_data) in uart_mvebu_bus_probe()
484 device_set_desc(sc->sc_dev, "Marvell Armada 3700 UART"); in uart_mvebu_bus_probe()
486 sc->sc_txfifosz = 32; in uart_mvebu_bus_probe()
487 sc->sc_rxfifosz = 64; in uart_mvebu_bus_probe()
488 sc->sc_hwiflow = 0; in uart_mvebu_bus_probe()
489 sc->sc_hwoflow = 0; in uart_mvebu_bus_probe()
499 int rx, er; in uart_mvebu_bus_receive() local
501 bas = &sc->sc_bas; in uart_mvebu_bus_receive()
502 uart_lock(sc->sc_hwmtx); in uart_mvebu_bus_receive()
506 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; in uart_mvebu_bus_receive()
511 rx = xc & 0xff; in uart_mvebu_bus_receive()
522 uart_rx_put(sc, rx | er); in uart_mvebu_bus_receive()
528 * RX FIFO in uart_mvebu_bus_receive()
535 uart_unlock(sc->sc_hwmtx); in uart_mvebu_bus_receive()
550 int i, ctrl; in uart_mvebu_bus_transmit() local
552 bas = &sc->sc_bas; in uart_mvebu_bus_transmit()
553 uart_lock(sc->sc_hwmtx); in uart_mvebu_bus_transmit()
556 ctrl = uart_getreg(bas, UART_CTRL); in uart_mvebu_bus_transmit()
557 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK); in uart_mvebu_bus_transmit()
560 for (i = 0; i < sc->sc_txdatasz; i++) { in uart_mvebu_bus_transmit()
561 uart_setreg(bas, UART_TSH, sc->sc_txbuf[i] & 0xff); in uart_mvebu_bus_transmit()
569 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_IDLE_INT); in uart_mvebu_bus_transmit()
573 sc->sc_txbusy = 1; in uart_mvebu_bus_transmit()
575 uart_unlock(sc->sc_hwmtx); in uart_mvebu_bus_transmit()
583 struct uart_bas *bas = &sc->sc_bas; in uart_mvebu_bus_grab()
584 uint32_t ctrl; in uart_mvebu_bus_grab() local
587 uart_lock(sc->sc_hwmtx); in uart_mvebu_bus_grab()
588 ctrl = uart_getreg(bas, UART_CTRL); in uart_mvebu_bus_grab()
589 msc->intrm = ctrl & CTRL_INTR_MASK; in uart_mvebu_bus_grab()
590 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK); in uart_mvebu_bus_grab()
592 uart_unlock(sc->sc_hwmtx); in uart_mvebu_bus_grab()
599 struct uart_bas *bas = &sc->sc_bas; in uart_mvebu_bus_ungrab()
600 uint32_t ctrl; in uart_mvebu_bus_ungrab() local
603 uart_lock(sc->sc_hwmtx); in uart_mvebu_bus_ungrab()
604 ctrl = uart_getreg(bas, UART_CTRL) & ~CTRL_INTR_MASK; in uart_mvebu_bus_ungrab()
605 uart_setreg(bas, UART_CTRL, ctrl | msc->intrm); in uart_mvebu_bus_ungrab()
607 uart_unlock(sc->sc_hwmtx); in uart_mvebu_bus_ungrab()