1 /*-
61 #define	CTRL_TX_HALF_INT	(1 << 8)	/* TX Half-Full Interrupt Enable */
62 #define	CTRL_RX_HALF_INT	(1 << 7)	/* RX Half-Full Interrupt Enable */
127  * Low-level UART interface.
152 uart_mvebu_divisor(int rclk, int baudrate)  in uart_mvebu_divisor()  argument
159 	divisor = (rclk >> 4) / baudrate;  in uart_mvebu_divisor()
199 		divisor = uart_mvebu_divisor(bas->rclk, baudrate);  in uart_mvebu_param()
225 	bas->rclk = DEFAULT_RCLK;  in uart_mvebu_init()
306 	"mvebu-uart",
317 	{"marvell,armada-3700-uart",	(uintptr_t)&uart_mvebu_class},
328 	bas = &sc->sc_bas;  in uart_mvebu_bus_attach()
329 	uart_lock(sc->sc_hwmtx);  in uart_mvebu_bus_attach()
341 	uart_unlock(sc->sc_hwmtx);  in uart_mvebu_bus_attach()
359 	bas = &sc->sc_bas;  in uart_mvebu_bus_flush()
360 	uart_lock(sc->sc_hwmtx);  in uart_mvebu_bus_flush()
385 	uart_unlock(sc->sc_hwmtx);  in uart_mvebu_bus_flush()
403 	bas = &sc->sc_bas;  in uart_mvebu_bus_ioctl()
404 	uart_lock(sc->sc_hwmtx);  in uart_mvebu_bus_ioctl()
418 		baudrate = bas->rclk/(divisor * 16);  in uart_mvebu_bus_ioctl()
426 	uart_unlock(sc->sc_hwmtx);  in uart_mvebu_bus_ioctl()
437 	bas = &sc->sc_bas;  in uart_mvebu_bus_ipend()
438 	uart_lock(sc->sc_hwmtx);  in uart_mvebu_bus_ipend()
457 	uart_unlock(sc->sc_hwmtx);  in uart_mvebu_bus_ipend()
468 	uart_lock(sc->sc_hwmtx);  in uart_mvebu_bus_param()
469 	ret = uart_mvebu_param(&sc->sc_bas, baudrate, databits, stopbits, parity);  in uart_mvebu_bus_param()
470 	uart_unlock(sc->sc_hwmtx);  in uart_mvebu_bus_param()
478 	if (!ofw_bus_status_okay(sc->sc_dev))  in uart_mvebu_bus_probe()
481 	if (!ofw_bus_search_compatible(sc->sc_dev, compat_data)->ocd_data)  in uart_mvebu_bus_probe()
484 	device_set_desc(sc->sc_dev, "Marvell Armada 3700 UART");  in uart_mvebu_bus_probe()
486 	sc->sc_txfifosz = 32;  in uart_mvebu_bus_probe()
487 	sc->sc_rxfifosz = 64;  in uart_mvebu_bus_probe()
488 	sc->sc_hwiflow = 0;  in uart_mvebu_bus_probe()
489 	sc->sc_hwoflow = 0;  in uart_mvebu_bus_probe()
501 	bas = &sc->sc_bas;  in uart_mvebu_bus_receive()
502 	uart_lock(sc->sc_hwmtx);  in uart_mvebu_bus_receive()
506 			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;  in uart_mvebu_bus_receive()
535 	uart_unlock(sc->sc_hwmtx);  in uart_mvebu_bus_receive()
552 	bas = &sc->sc_bas;  in uart_mvebu_bus_transmit()
553 	uart_lock(sc->sc_hwmtx);  in uart_mvebu_bus_transmit()
560 	for (i = 0; i < sc->sc_txdatasz; i++) {  in uart_mvebu_bus_transmit()
561 		uart_setreg(bas, UART_TSH, sc->sc_txbuf[i] & 0xff);  in uart_mvebu_bus_transmit()
573 	sc->sc_txbusy = 1;  in uart_mvebu_bus_transmit()
575 	uart_unlock(sc->sc_hwmtx);  in uart_mvebu_bus_transmit()
583 	struct uart_bas *bas = &sc->sc_bas;  in uart_mvebu_bus_grab()
587 	uart_lock(sc->sc_hwmtx);  in uart_mvebu_bus_grab()
589 	msc->intrm = ctrl & CTRL_INTR_MASK;  in uart_mvebu_bus_grab()
592 	uart_unlock(sc->sc_hwmtx);  in uart_mvebu_bus_grab()
599 	struct uart_bas *bas = &sc->sc_bas;  in uart_mvebu_bus_ungrab()
603 	uart_lock(sc->sc_hwmtx);  in uart_mvebu_bus_ungrab()
605 	uart_setreg(bas, UART_CTRL, ctrl | msc->intrm);  in uart_mvebu_bus_ungrab()
607 	uart_unlock(sc->sc_hwmtx);  in uart_mvebu_bus_ungrab()