Lines Matching +full:rclk +full:-
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
77 di->bas.chan = 0; in uart_cpu_acpi_init_devinfo()
78 di->bas.rclk = 0; in uart_cpu_acpi_init_devinfo()
79 di->databits = 8; in uart_cpu_acpi_init_devinfo()
80 di->stopbits = 1; in uart_cpu_acpi_init_devinfo()
81 di->parity = UART_PARITY_NONE; in uart_cpu_acpi_init_devinfo()
82 di->ops = uart_getops(class); in uart_cpu_acpi_init_devinfo()
85 switch (addr->SpaceId) { in uart_cpu_acpi_init_devinfo()
87 di->bas.bst = uart_bus_space_mem; in uart_cpu_acpi_init_devinfo()
90 di->bas.bst = uart_bus_space_io; in uart_cpu_acpi_init_devinfo()
94 (int)addr->SpaceId); in uart_cpu_acpi_init_devinfo()
97 switch (addr->AccessWidth) { in uart_cpu_acpi_init_devinfo()
101 di->bas.regiowidth = 1; in uart_cpu_acpi_init_devinfo()
104 di->bas.regiowidth = 2; in uart_cpu_acpi_init_devinfo()
107 di->bas.regiowidth = 4; in uart_cpu_acpi_init_devinfo()
110 di->bas.regiowidth = 8; in uart_cpu_acpi_init_devinfo()
114 (int)addr->AccessWidth); in uart_cpu_acpi_init_devinfo()
117 switch (addr->BitWidth) { in uart_cpu_acpi_init_devinfo()
121 di->bas.regshft = 0; in uart_cpu_acpi_init_devinfo()
124 di->bas.regshft = 1; in uart_cpu_acpi_init_devinfo()
127 di->bas.regshft = 2; in uart_cpu_acpi_init_devinfo()
130 di->bas.regshft = 3; in uart_cpu_acpi_init_devinfo()
134 (int)addr->BitWidth); in uart_cpu_acpi_init_devinfo()
161 cd = uart_cpu_acpi_scan(spcr->InterfaceType); in uart_cpu_acpi_spcr()
164 class = cd->cd_class; in uart_cpu_acpi_spcr()
166 error = uart_cpu_acpi_init_devinfo(di, class, &spcr->SerialPort); in uart_cpu_acpi_spcr()
175 if (spcr->Header.Revision >= 4 && spcr->PreciseBaudrate != 0) { in uart_cpu_acpi_spcr()
176 di->baudrate = spcr->PreciseBaudrate; in uart_cpu_acpi_spcr()
178 switch (spcr->BaudRate) { in uart_cpu_acpi_spcr()
181 di->baudrate = 0; in uart_cpu_acpi_spcr()
184 di->baudrate = 9600; in uart_cpu_acpi_spcr()
187 di->baudrate = 19200; in uart_cpu_acpi_spcr()
190 di->baudrate = 57600; in uart_cpu_acpi_spcr()
193 di->baudrate = 115200; in uart_cpu_acpi_spcr()
197 (int)spcr->BaudRate); in uart_cpu_acpi_spcr()
203 * Rev 3 and newer can specify a rclk, use it if it's there. It's in uart_cpu_acpi_spcr()
204 * defined to be 0 when it's not known, and we've initialized rclk to 0 in uart_cpu_acpi_spcr()
207 if (spcr->Header.Revision >= 3) in uart_cpu_acpi_spcr()
208 di->bas.rclk = spcr->UartClkFreq; in uart_cpu_acpi_spcr()
211 * If no rclk is set, then we will assume the BIOS has configured the in uart_cpu_acpi_spcr()
212 * hardware at the stated baudrate, so we can use it to guess the rclk in uart_cpu_acpi_spcr()
215 if (di->bas.rclk == 0) in uart_cpu_acpi_spcr()
216 di->bas.rclk_guess = 1; in uart_cpu_acpi_spcr()
218 if (spcr->PciVendorId != PCIV_INVALID && in uart_cpu_acpi_spcr()
219 spcr->PciDeviceId != PCIV_INVALID) { in uart_cpu_acpi_spcr()
220 di->pci_info.vendor = spcr->PciVendorId; in uart_cpu_acpi_spcr()
221 di->pci_info.device = spcr->PciDeviceId; in uart_cpu_acpi_spcr()
225 error = bus_space_map(di->bas.bst, spcr->SerialPort.Address, in uart_cpu_acpi_spcr()
226 uart_getrange(class), 0, &di->bas.bsh); in uart_cpu_acpi_spcr()
258 dbg2_dev = (ACPI_DBG2_DEVICE *)((uintptr_t)dbg2 + dbg2->InfoOffset); in uart_cpu_acpi_dbg2()
260 while ((uintptr_t)dbg2_dev + dbg2_dev->Length <= in uart_cpu_acpi_dbg2()
261 (uintptr_t)dbg2 + dbg2->Header.Length) { in uart_cpu_acpi_dbg2()
262 if (dbg2_dev->PortType != ACPI_DBG2_SERIAL_PORT) in uart_cpu_acpi_dbg2()
266 if (dbg2_dev->RegisterCount != 1) in uart_cpu_acpi_dbg2()
269 cd = uart_cpu_acpi_scan(dbg2_dev->PortSubtype); in uart_cpu_acpi_dbg2()
273 class = cd->cd_class; in uart_cpu_acpi_dbg2()
275 ((uintptr_t)dbg2_dev + dbg2_dev->BaseAddressOffset); in uart_cpu_acpi_dbg2()
285 ((uintptr_t)dbg2_dev + dbg2_dev->Length); in uart_cpu_acpi_dbg2()
291 di->baudrate = 115200; in uart_cpu_acpi_dbg2()
294 error = bus_space_map(di->bas.bst, base_address->Address, in uart_cpu_acpi_dbg2()
295 uart_getrange(class), 0, &di->bas.bsh); in uart_cpu_acpi_dbg2()