Lines Matching +full:rclk +full:-
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
36 * to access the UART. The rclk field, although not important to actually
44 u_int rclk; member
48 u_int rclk_guess;/* if rclk == 0, use baud + divisor to compute rclk */
51 #define uart_regofs(bas, reg) ((reg) << (bas)->regshft)
52 #define uart_regiowidth(bas) ((bas)->regiowidth)
62 ret = bus_space_read_8(bas->bst, bas->bsh, uart_regofs(bas, reg)); in uart_getreg()
66 ret = bus_space_read_4(bas->bst, bas->bsh, uart_regofs(bas, reg)); in uart_getreg()
69 ret = bus_space_read_2(bas->bst, bas->bsh, uart_regofs(bas, reg)); in uart_getreg()
72 ret = bus_space_read_1(bas->bst, bas->bsh, uart_regofs(bas, reg)); in uart_getreg()
86 bus_space_write_8(bas->bst, bas->bsh, uart_regofs(bas, reg), value); in uart_setreg()
90 bus_space_write_4(bas->bst, bas->bsh, uart_regofs(bas, reg), value); in uart_setreg()
93 bus_space_write_2(bas->bst, bas->bsh, uart_regofs(bas, reg), value); in uart_setreg()
96 bus_space_write_1(bas->bst, bas->bsh, uart_regofs(bas, reg), value); in uart_setreg()
107 bus_space_barrier((bas)->bst, (bas)->bsh, 0, 0, \