Lines Matching +full:0 +full:x40a
39 #define TWS_BIT0 0x00000001
40 #define TWS_BIT1 0x00000002
41 #define TWS_BIT2 0x00000004
42 #define TWS_BIT3 0x00000008
43 #define TWS_BIT4 0x00000010
44 #define TWS_BIT5 0x00000020
45 #define TWS_BIT6 0x00000040
46 #define TWS_BIT7 0x00000080
47 #define TWS_BIT8 0x00000100
48 #define TWS_BIT9 0x00000200
49 #define TWS_BIT10 0x00000400
50 #define TWS_BIT11 0x00000800
51 #define TWS_BIT12 0x00001000
52 #define TWS_BIT13 0x00002000
53 #define TWS_BIT14 0x00004000
54 #define TWS_BIT15 0x00008000
55 #define TWS_BIT16 0x00010000
56 #define TWS_BIT17 0x00020000
57 #define TWS_BIT18 0x00040000
58 #define TWS_BIT19 0x00080000
59 #define TWS_BIT20 0x00100000
60 #define TWS_BIT21 0x00200000
61 #define TWS_BIT22 0x00400000
62 #define TWS_BIT23 0x00800000
63 #define TWS_BIT24 0x01000000
64 #define TWS_BIT25 0x02000000
65 #define TWS_BIT26 0x04000000
66 #define TWS_BIT27 0x08000000
67 #define TWS_BIT28 0x10000000
68 #define TWS_BIT29 0x20000000
69 #define TWS_BIT30 0x40000000
70 #define TWS_BIT31 0x80000000
76 #define TWS_SENSE_SCSI_CURRENT_ERROR 0x70
77 #define TWS_SENSE_SCSI_DEFERRED_ERROR 0x71
95 #define TWS_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a
96 #define TWS_ERROR_NOT_SUPPORTED 0x010D
97 #define TWS_ERROR_UNIT_OFFLINE 0x0128
98 #define TWS_ERROR_MORE_DATA 0x0231
101 #define TWS_AEN_QUEUE_EMPTY 0x00
102 #define TWS_AEN_SOFT_RESET 0x01
103 #define TWS_AEN_SYNC_TIME_WITH_HOST 0x31
106 #define TWS_SEVERITY_ERROR 0x1
107 #define TWS_SEVERITY_WARNING 0x2
108 #define TWS_SEVERITY_INFO 0x3
109 #define TWS_SEVERITY_DEBUG 0x4
111 #define TWS_64BIT_SG_ADDRESSES 0x00000001
112 #define TWS_BIT_EXTEND 0x00000002
115 #define TWS_BASE_FW_BRANCH 0
121 #define TWS_CURRENT_ARCH_ID 0x000A
123 #define TWS_FIFO_EMPTY 0xFFFFFFFFFFFFFFFFull
124 #define TWS_FIFO_EMPTY32 0xFFFFFFFFull
127 #define TWS_CONTROL_REGISTER_OFFSET 0x0
128 #define TWS_STATUS_REGISTER_OFFSET 0x4
129 #define TWS_COMMAND_QUEUE_OFFSET 0x8
130 #define TWS_RESPONSE_QUEUE_OFFSET 0xC
131 #define TWS_COMMAND_QUEUE_OFFSET_LOW 0x20
132 #define TWS_COMMAND_QUEUE_OFFSET_HIGH 0x24
133 #define TWS_LARGE_RESPONSE_QUEUE_OFFSET 0x30
136 #define TWS_I2O0_STATUS 0x0
138 #define TWS_I2O0_HIBDB 0x20
140 #define TWS_I2O0_HISTAT 0x30
141 #define TWS_I2O0_HIMASK 0x34
143 #define TWS_I2O0_HIBQP 0x40
144 #define TWS_I2O0_HOBQP 0x44
146 #define TWS_I2O0_CTL 0x74
148 #define TWS_I2O0_IOBDB 0x9C
149 #define TWS_I2O0_HOBDBC 0xA0
151 #define TWS_I2O0_SCRPD3 0xBC
153 #define TWS_I2O0_HIBQPL 0xC0 /* 64bit inb port low */
154 #define TWS_I2O0_HIBQPH 0xC4 /* 64bit inb port high */
155 #define TWS_I2O0_HOBQPL 0xC8 /* 64bit out port low */
156 #define TWS_I2O0_HOBQPH 0xCC /* 64bit out port high */
159 #define TWS_I2O0_IOPOBQPL 0xD8 /* OBFL */
160 #define TWS_I2O0_IOPOBQPH 0xDC /* OBFH */
161 #define TWS_I2O0_SRC_ADDRH 0xF8 /* Msg ASA */
163 #define TWS_MSG_ACC_MASK 0x20000000
164 #define TWS_32BIT_MASK 0xFFFFFFFF
167 #define TWS_FW_CMD_NOP 0x0
168 #define TWS_FW_CMD_INIT_CONNECTION 0x01
169 #define TWS_FW_CMD_EXECUTE_SCSI 0x10
171 #define TWS_FW_CMD_ATA_PASSTHROUGH 0x11 // This is really a PASSTHROUGH for both ATA and SC…
172 #define TWS_FW_CMD_GET_PARAM 0x12
173 #define TWS_FW_CMD_SET_PARAM 0x13
176 ((sgl_off << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */
179 ((res << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */
182 (sgl_off__opcode & 0x1F) /* 3:5 */
187 #define TWS_PARAM_VERSION_TABLE 0x0402
192 #define TWS_PARAM_CONTROLLER_TABLE 0x0403
195 #define TWS_PARAM_TIME_TABLE 0x40A
196 #define TWS_PARAM_TIME_SCHED_TIME 0x3
198 #define TWS_PARAM_PHYS_TABLE 0x0001
201 #define TWS_9K_PARAM_DESCRIPTOR 0x8000
335 u_int32_t status :8; /* should be 0 */