1 /*-
54 #define	TPM_LOC_STATE_ESTB		BIT(0)
55 #define	TPM_LOC_STATE_ASSIGNED		BIT(1)
57 #define	TPM_LOC_STATE_VALID		BIT(7)
62 #define	TPM_LOC_CTRL_REQUEST		BIT(0)
63 #define	TPM_LOC_CTRL_RELINQUISH		BIT(1)
65 #define	TPM_CRB_CTRL_REQ_GO_READY	BIT(0)
66 #define	TPM_CRB_CTRL_REQ_GO_IDLE	BIT(1)
68 #define	TPM_CRB_CTRL_STS_ERR_BIT	BIT(0)
69 #define	TPM_CRB_CTRL_STS_IDLE_BIT	BIT(1)
74 #define	TPM_CRB_CTRL_START_CMD		BIT(0)
76 #define	TPM_CRB_INT_ENABLE_BIT		BIT(31)
95     uint32_t mask, uint32_t val, int32_t timeout);
114 	   tbl->StartMethod != TPM2_START_METHOD_CRB)  in tpmcrb_acpi_probe()
130 	if (res->Type != ACPI_RESOURCE_TYPE_FIXED_MEMORY32)  in tpmcrb_fix_buff_offsets()
133 	base_addr = res->Data.FixedMemory32.Address;  in tpmcrb_fix_buff_offsets()
134 	length = res->Data.FixedMemory32.AddressLength;  in tpmcrb_fix_buff_offsets()
136 	if (crb_sc->cmd_off > base_addr && crb_sc->cmd_off < base_addr + length)  in tpmcrb_fix_buff_offsets()
137 		crb_sc->cmd_off -= base_addr;  in tpmcrb_fix_buff_offsets()
138 	if (crb_sc->rsp_off > base_addr && crb_sc->rsp_off < base_addr + length)  in tpmcrb_fix_buff_offsets()
139 		crb_sc->rsp_off -= base_addr;  in tpmcrb_fix_buff_offsets()
154 	sc = &crb_sc->base;  in tpmcrb_attach()
156 	sc->dev = dev;  in tpmcrb_attach()
158 	sx_init(&sc->dev_lock, "TPM driver lock");  in tpmcrb_attach()
159 	sc->buf = malloc(TPM_BUFSIZE, M_TPM20, M_WAITOK);  in tpmcrb_attach()
161 	sc->mem_rid = 0;  in tpmcrb_attach()
162 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,  in tpmcrb_attach()
164 	if (sc->mem_res == NULL) {  in tpmcrb_attach()
179 	sc->interrupts = false;  in tpmcrb_attach()
188 	crb_sc->rsp_off = TPM_READ_8(sc->dev, TPM_CRB_CTRL_RSP_ADDR);  in tpmcrb_attach()
190 	crb_sc->rsp_off = TPM_READ_4(sc->dev, TPM_CRB_CTRL_RSP_ADDR);  in tpmcrb_attach()
191 	crb_sc->rsp_off |= ((uint64_t) TPM_READ_4(sc->dev, TPM_CRB_CTRL_RSP_HADDR) << 32);  in tpmcrb_attach()
193 	crb_sc->cmd_off = TPM_READ_4(sc->dev, TPM_CRB_CTRL_CMD_LADDR);  in tpmcrb_attach()
194 	crb_sc->cmd_off |= ((uint64_t) TPM_READ_4(sc->dev, TPM_CRB_CTRL_CMD_HADDR) << 32);  in tpmcrb_attach()
195 	crb_sc->cmd_buf_size = TPM_READ_4(sc->dev, TPM_CRB_CTRL_CMD_SIZE);  in tpmcrb_attach()
196 	crb_sc->rsp_buf_size = TPM_READ_4(sc->dev, TPM_CRB_CTRL_RSP_SIZE);  in tpmcrb_attach()
208 	if (crb_sc->rsp_off == crb_sc->cmd_off) {  in tpmcrb_attach()
213 		if (crb_sc->cmd_buf_size != crb_sc->rsp_buf_size) {  in tpmcrb_attach()
214 			device_printf(sc->dev,  in tpmcrb_attach()
236 	if (sc->mem_res != NULL)  in tpmcrb_detach()
238 		    sc->mem_rid, sc->mem_res);  in tpmcrb_detach()
244 tpm_wait_for_u32(struct tpm_sc *sc, bus_size_t off, uint32_t mask, uint32_t val,  in tpm_wait_for_u32()  argument
249 	if ((TPM_READ_4(sc->dev, off) & mask) == val)  in tpm_wait_for_u32()
253 		if ((TPM_READ_4(sc->dev, off) & mask) == val)  in tpm_wait_for_u32()
257 		timeout -= tick;  in tpm_wait_for_u32()
265 	uint32_t mask;  in tpmcrb_request_locality()  local
271 	mask = TPM_LOC_STATE_VALID | TPM_LOC_STATE_ASSIGNED;  in tpmcrb_request_locality()
274 	if (!tpm_wait_for_u32(sc, TPM_LOC_STATE, mask, mask, TPM_TIMEOUT_C))  in tpmcrb_request_locality()
290 	uint32_t mask = ~0;  in tpmcrb_cancel_cmd()  local
292 	TPM_WRITE_4(sc->dev, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CMD);  in tpmcrb_cancel_cmd()
294 		    mask, ~mask, TPM_TIMEOUT_B)) {  in tpmcrb_cancel_cmd()
295 		device_printf(sc->dev,  in tpmcrb_cancel_cmd()
300 	TPM_WRITE_4(sc->dev, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CLEAR);  in tpmcrb_cancel_cmd()
308 	int mask, timeout;  in tpmcrb_state_idle()  local
312 	sc = &crb_sc->base;  in tpmcrb_state_idle()
316 		mask = TPM_CRB_CTRL_STS_IDLE_BIT;  in tpmcrb_state_idle()
317 		if (!tpm_wait_for_u32(sc, TPM_CRB_CTRL_STS, mask, mask,  in tpmcrb_state_idle()
329 	int mask, timeout;  in tpmcrb_state_ready()  local
333 	sc = &crb_sc->base;  in tpmcrb_state_ready()
337 		mask = TPM_CRB_CTRL_REQ_GO_READY;  in tpmcrb_state_ready()
338 		if (!tpm_wait_for_u32(sc, TPM_CRB_CTRL_STS, mask, !mask,  in tpmcrb_state_ready()
351 	uint32_t mask, curr_cmd;  in tpmcrb_transmit()  local
355 	sc = &crb_sc->base;  in tpmcrb_transmit()
357 	sx_assert(&sc->dev_lock, SA_XLOCKED);  in tpmcrb_transmit()
359 	if (length > crb_sc->cmd_buf_size) {  in tpmcrb_transmit()
367 		    "Device has Error bit set\n");  in tpmcrb_transmit()
375 	/* Clear cancellation bit */  in tpmcrb_transmit()
396 	 * Command code is passed in bytes 6-10.  in tpmcrb_transmit()
398 	curr_cmd = be32toh(*(uint32_t *) (&sc->buf[6]));  in tpmcrb_transmit()
402 	bus_write_region_stream_1(sc->mem_res, crb_sc->cmd_off,  in tpmcrb_transmit()
403 	    sc->buf, length);  in tpmcrb_transmit()
404 	TPM_WRITE_BARRIER(dev, crb_sc->cmd_off, length);  in tpmcrb_transmit()
409 	mask = ~0;  in tpmcrb_transmit()
410 	if (!tpm_wait_for_u32(sc, TPM_CRB_CTRL_START, mask, ~mask, timeout)) {  in tpmcrb_transmit()
417 	/* Read response header. Length is passed in bytes 2 - 6. */  in tpmcrb_transmit()
418 	bus_read_region_stream_1(sc->mem_res, crb_sc->rsp_off,  in tpmcrb_transmit()
419 	    sc->buf, TPM_HEADER_SIZE);  in tpmcrb_transmit()
420 	bytes_available = be32toh(*(uint32_t *) (&sc->buf[2]));  in tpmcrb_transmit()
429 	bus_read_region_stream_1(sc->mem_res, crb_sc->rsp_off + TPM_HEADER_SIZE,  in tpmcrb_transmit()
430 	      &sc->buf[TPM_HEADER_SIZE], bytes_available - TPM_HEADER_SIZE);  in tpmcrb_transmit()
434 		    "Failed to transition to idle state post-send\n");  in tpmcrb_transmit()
439 	sc->pending_data_length = bytes_available;  in tpmcrb_transmit()
440 	sc->total_length = bytes_available;  in tpmcrb_transmit()