Lines Matching +full:0 +full:x50c
45 #define TI_PCI_ID 0x000 /* PCI device/vendor ID */
46 #define TI_PCI_CMDSTAT 0x004
47 #define TI_PCI_CLASSCODE 0x008
48 #define TI_PCI_BIST 0x00C
49 #define TI_PCI_LOMEM 0x010 /* Shared memory base address */
50 #define TI_PCI_SUBSYS 0x02C
51 #define TI_PCI_ROMBASE 0x030
52 #define TI_PCI_INT 0x03C
55 #define PCIM_CMD_MWIEN 0x0010
61 #define ALT_VENDORID 0x12AE
62 #define ALT_DEVICEID_ACENIC 0x0001
63 #define ALT_DEVICEID_ACENIC_COPPER 0x0002
68 #define TC_VENDORID 0x10B7
69 #define TC_DEVICEID_3C985 0x0001
74 #define NG_VENDORID 0x1385
75 #define NG_DEVICEID_GA620 0x620A
76 #define NG_DEVICEID_GA620T 0x630A
81 #define SGI_VENDORID 0x10A9
82 #define SGI_DEVICEID_TIGON 0x0009
88 #define DEC_VENDORID 0x1011
89 #define DEC_DEVICEID_FARALLON_PN9000SX 0x001a
94 #define TI_MISC_HOST_CTL 0x040
95 #define TI_MISC_LOCAL_CTL 0x044
96 #define TI_SEM_AB 0x048 /* Tigon 2 only */
97 #define TI_MISC_CONF 0x050 /* Tigon 2 only */
98 #define TI_TIMER_BITS 0x054
99 #define TI_TIMERREF 0x058
100 #define TI_PCI_STATE 0x05C
101 #define TI_MAIN_EVENT_A 0x060
102 #define TI_MAILBOX_EVENT_A 0x064
103 #define TI_WINBASE 0x068
104 #define TI_WINDATA 0x06C
105 #define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */
106 #define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */
107 #define TI_TIMERREF_B 0x078 /* Tigon 2 only */
108 #define TI_SERIAL 0x07C
113 #define TI_MHC_INTSTATE 0x00000001
114 #define TI_MHC_CLEARINT 0x00000002
115 #define TI_MHC_RESET 0x00000008
116 #define TI_MHC_BYTE_SWAP_ENB 0x00000010
117 #define TI_MHC_WORD_SWAP_ENB 0x00000020
118 #define TI_MHC_MASK_INTS 0x00000040
119 #define TI_MHC_CHIP_REV_MASK 0xF0000000
132 #define TI_REV_TIGON_I 0x40000000
133 #define TI_REV_TIGON_II 0x60000000
138 #define TI_FIRMWARE_MAJOR 0xc
139 #define TI_FIRMWARE_MINOR 0x4
140 #define TI_FIRMWARE_FIX 0xb
145 #define TI_MLC_EE_WRITE_ENB 0x00000010
146 #define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */
147 #define TI_MLC_LOCALADDR_21 0x00004000
148 #define TI_MLC_LOCALADDR_22 0x00008000
149 #define TI_MLC_SBUS_WRITEERR 0x00080000
150 #define TI_MLC_EE_CLK 0x00100000
151 #define TI_MLC_EE_TXEN 0x00200000
152 #define TI_MLC_EE_DOUT 0x00400000
153 #define TI_MLC_EE_DIN 0x00800000
156 #define TI_MLC_SRAM_BANK_DISA 0x00000000
157 #define TI_MLC_SRAM_BANK_1024K 0x00000100
158 #define TI_MLC_SRAM_BANK_512K 0x00000200
159 #define TI_MLC_SRAM_BANK_256K 0x00000300
164 #define TI_EE_MAC_OFFSET 0x8c
166 #define TI_DMA_ASSIST 0x11C
167 #define TI_CPU_STATE 0x140
168 #define TI_CPU_PROGRAM_COUNTER 0x144
169 #define TI_SRAM_ADDR 0x154
170 #define TI_SRAM_DATA 0x158
171 #define TI_GEN_0 0x180
172 #define TI_GEN_X 0x1FC
173 #define TI_MAC_TX_STATE 0x200
174 #define TI_MAC_RX_STATE 0x220
175 #define TI_CPU_CTL_B 0x240 /* Tigon 2 only */
176 #define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */
177 #define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */
178 #define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */
179 #define TI_GEN_B_0 0x280 /* Tigon 2 only */
180 #define TI_GEN_B_X 0x2FC /* Tigon 2 only */
185 #define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */
190 #define TI_PCISTATE_FORCE_RESET 0x00000001
191 #define TI_PCISTATE_PROVIDE_LEN 0x00000002
192 #define TI_PCISTATE_READ_MAXDMA 0x0000001C
193 #define TI_PCISTATE_WRITE_MAXDMA 0x000000E0
194 #define TI_PCISTATE_MINDMA 0x0000FF00
195 #define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000
196 #define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000
197 #define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000
198 #define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000
199 #define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */
200 #define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */
201 #define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */
202 #define TI_PCISTATE_READ_CMD 0x0F000000
203 #define TI_PCISTATE_WRITE_CMD 0xF0000000
205 #define TI_PCI_READMAX_4 0x04
206 #define TI_PCI_READMAX_16 0x08
207 #define TI_PCI_READMAX_32 0x0C
208 #define TI_PCI_READMAX_64 0x10
209 #define TI_PCI_READMAX_128 0x14
210 #define TI_PCI_READMAX_256 0x18
211 #define TI_PCI_READMAX_1024 0x1C
213 #define TI_PCI_WRITEMAX_4 0x20
214 #define TI_PCI_WRITEMAX_16 0x40
215 #define TI_PCI_WRITEMAX_32 0x60
216 #define TI_PCI_WRITEMAX_64 0x80
217 #define TI_PCI_WRITEMAX_128 0xA0
218 #define TI_PCI_WRITEMAX_256 0xC0
219 #define TI_PCI_WRITEMAX_1024 0xE0
221 #define TI_PCI_READ_CMD 0x06000000
222 #define TI_PCI_WRITE_CMD 0x70000000
227 #define TI_DMASTATE_ENABLE 0x00000001
228 #define TI_DMASTATE_PAUSE 0x00000002
233 #define TI_CPUSTATE_RESET 0x00000001
234 #define TI_CPUSTATE_STEP 0x00000002
235 #define TI_CPUSTATE_ROMFAIL 0x00000010
236 #define TI_CPUSTATE_HALT 0x00010000
240 #define TI_TXSTATE_RESET 0x00000001
241 #define TI_TXSTATE_ENB 0x00000002
242 #define TI_TXSTATE_STOP 0x00000004
247 #define TI_RXSTATE_RESET 0x00000001
248 #define TI_RXSTATE_ENB 0x00000002
249 #define TI_RXSTATE_STOP 0x00000004
256 #define TI_MB_HOSTINTR_HI 0x500
257 #define TI_MB_HOSTINTR_LO 0x504
259 #define TI_MB_CMDPROD_IDX_HI 0x508
260 #define TI_MB_CMDPROD_IDX_LO 0x50C
262 #define TI_MB_SENDPROD_IDX_HI 0x510
263 #define TI_MB_SENDPROD_IDX_LO 0x514
265 #define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */
266 #define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */
268 #define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */
269 #define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */
271 #define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */
272 #define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */
274 #define TI_MB_RSVD 0x530
282 * The NIC internally maps these registers starting at address 0,
284 * subtract 0x600 (the address of the first register).
287 #define TI_GCR_BASE 0x600
288 #define TI_GCR_MACADDR 0x600
289 #define TI_GCR_PAR0 0x600
290 #define TI_GCR_PAR1 0x604
291 #define TI_GCR_GENINFO_HI 0x608
292 #define TI_GCR_GENINFO_LO 0x60C
293 #define TI_GCR_MCASTADDR 0x610 /* obsolete */
294 #define TI_GCR_MAR0 0x610 /* obsolete */
295 #define TI_GCR_MAR1 0x614 /* obsolete */
296 #define TI_GCR_OPMODE 0x618
297 #define TI_GCR_DMA_READCFG 0x61C
298 #define TI_GCR_DMA_WRITECFG 0x620
299 #define TI_GCR_TX_BUFFER_RATIO 0x624
300 #define TI_GCR_EVENTCONS_IDX 0x628
301 #define TI_GCR_CMDCONS_IDX 0x62C
302 #define TI_GCR_TUNEPARMS 0x630
303 #define TI_GCR_RX_COAL_TICKS 0x630
304 #define TI_GCR_TX_COAL_TICKS 0x634
305 #define TI_GCR_STAT_TICKS 0x638
306 #define TI_GCR_TX_MAX_COAL_BD 0x63C
307 #define TI_GCR_RX_MAX_COAL_BD 0x640
308 #define TI_GCR_NIC_TRACING 0x644
309 #define TI_GCR_GLINK 0x648
310 #define TI_GCR_LINK 0x64C
311 #define TI_GCR_NICTRACE_PTR 0x650
312 #define TI_GCR_NICTRACE_START 0x654
313 #define TI_GCR_NICTRACE_LEN 0x658
314 #define TI_GCR_IFINDEX 0x65C
315 #define TI_GCR_IFMTU 0x660
316 #define TI_GCR_MASK_INTRS 0x664
317 #define TI_GCR_GLINK_STAT 0x668
318 #define TI_GCR_LINK_STAT 0x66C
319 #define TI_GCR_RXRETURNCONS_IDX 0x680
320 #define TI_GCR_CMDRING 0x700
330 #define TI_WINDOW 0x800
331 #define TI_WINLEN 0x800
338 #define TI_OPMODE_BYTESWAP_BD 0x00000002
339 #define TI_OPMODE_WORDSWAP_BD 0x00000004
340 #define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implemented */
341 #define TI_OPMODE_BYTESWAP_DATA 0x00000010
342 #define TI_OPMODE_1_DMA_ACTIVE 0x00000040
343 #define TI_OPMODE_SBUS 0x00000100
344 #define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200
345 #define TI_OPMODE_INCLUDE_CRC 0x00000400
346 #define TI_OPMODE_RX_BADFRAMES 0x00000800
347 #define TI_OPMODE_NO_EVENT_INTRS 0x00001000
348 #define TI_OPMODE_NO_TX_INTRS 0x00002000
349 #define TI_OPMODE_NO_RX_INTRS 0x00004000
350 #define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implemented */
351 #define TI_OPMODE_JUMBO_HDRSPLIT 0x00008000
356 #define TI_DMA_STATE_THRESH_16W 0x00000100
357 #define TI_DMA_STATE_THRESH_8W 0x00000080
358 #define TI_DMA_STATE_THRESH_4W 0x00000040
359 #define TI_DMA_STATE_THRESH_2W 0x00000020
360 #define TI_DMA_STATE_THRESH_1W 0x00000010
362 #define TI_DMA_STATE_FORCE_32_BIT 0x00000008
367 #define TI_GLNK_SENSE_NO_BEG 0x00002000
368 #define TI_GLNK_LOOPBACK 0x00004000
369 #define TI_GLNK_PREF 0x00008000
370 #define TI_GLNK_1000MB 0x00040000
371 #define TI_GLNK_FULL_DUPLEX 0x00080000
372 #define TI_GLNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */
373 #define TI_GLNK_RX_FLOWCTL_Y 0x00800000
374 #define TI_GLNK_AUTONEGENB 0x20000000
375 #define TI_GLNK_ENB 0x40000000
380 #define TI_LNK_LOOPBACK 0x00004000
381 #define TI_LNK_PREF 0x00008000
382 #define TI_LNK_10MB 0x00010000
383 #define TI_LNK_100MB 0x00020000
384 #define TI_LNK_1000MB 0x00040000
385 #define TI_LNK_FULL_DUPLEX 0x00080000
386 #define TI_LNK_HALF_DUPLEX 0x00100000
387 #define TI_LNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */
388 #define TI_LNK_RX_FLOWCTL_Y 0x00800000
389 #define TI_LNK_AUTONEGENB 0x20000000
390 #define TI_LNK_ENB 0x40000000
410 #define TI_TX_RING_BASE_128 0x3800
413 #define TI_TX_RING_BASE_256 0x3000
416 #define TI_TX_RING_BASE_512 0x2000
428 #define TI_MEM_MAX 0x7FFFFF
433 #define TI_REG_MAX 0x3fff
438 #define TI_BEG_SRAM 0x0 /* host thinks it's here */
439 #define TI_BEG_SCRATCH 0xc00000 /* beg of scratch pad area */
440 #define TI_END_SRAM_II 0x800000 /* end of SRAM, for 2 MB stuffed */
441 #define TI_END_SCRATCH_II 0xc04000 /* end of scratch pad CPU A (16KB) */
442 #define TI_END_SCRATCH_B 0xc02000 /* end of scratch pad CPU B (8KB) */
443 #define TI_BEG_SCRATCH_B_DEBUG 0xd00000 /* beg of scratch pad for ioctl */
444 #define TI_END_SCRATCH_B_DEBUG 0xd02000 /* end of scratch pad for ioctl */
445 #define TI_SCRATCH_DEBUG_OFF 0x100000 /* offset for ioctl usage */
446 #define TI_END_SRAM_I 0x200000 /* end of SRAM, for 2 MB stuffed */
447 #define TI_END_SCRATCH_I 0xc00800 /* end of scratch pad area (2KB) */
448 #define TI_BEG_PROM 0x40000000 /* beg of PROM, special access */
449 #define TI_BEG_FLASH 0x80000000 /* beg of EEPROM, special access */
450 #define TI_END_FLASH 0x80100000 /* end of EEPROM for 1 MB stuff */
451 #define TI_BEG_SER_EEPROM 0xa0000000 /* beg of Serial EEPROM (fake out) */
452 #define TI_END_SER_EEPROM 0xa0002000 /* end of Serial EEPROM (fake out) */
453 #define TI_BEG_REGS 0xc0000000 /* beg of register area */
454 #define TI_END_REGS 0xc0000400 /* end of register area */
455 #define TI_END_WRITE_REGS 0xc0000180 /* can't write GPRs currently */
456 #define TI_BEG_REGS2 0xc0000200 /* beg of second writeable reg area */
458 #define EEPROM_BYTE_LOC 0xff000000
463 #define TI_PROCESSOR_A 0
475 #define CPU_REG(reg, cpu) ((reg) + (cpu) * 0x100)
494 x->ti_addr_lo = baddr & 0xffffffff; in ti_hostaddr64()
514 * in the ring. It can be one of 2048, 1024 or 0 (which is the same as
530 #define TI_RCB_FLAG_TCP_UDP_CKSUM 0x00000001
531 #define TI_RCB_FLAG_IP_CKSUM 0x00000002
532 #define TI_RCB_FLAG_NO_PHDR_CKSUM 0x00000008
533 #define TI_RCB_FLAG_VLAN_ASSIST 0x00000010
534 #define TI_RCB_FLAG_COAL_UPD_ONLY 0x00000020
535 #define TI_RCB_FLAG_HOST_RING 0x00000040
536 #define TI_RCB_FLAG_IEEE_SNAP_CKSUM 0x00000080
537 #define TI_RCB_FLAG_USE_EXT_RX_BD 0x00000100
538 #define TI_RCB_FLAG_RING_DISABLED 0x00000200
711 #define TI_BDERR_CRC 0x0001
712 #define TI_BDERR_COLLDETECT 0x0002
713 #define TI_BDERR_LINKLOST 0x0004
714 #define TI_BDERR_DECODE 0x0008
715 #define TI_BDERR_ODD_NIBBLES 0x0010
716 #define TI_BDERR_MAC_ABRT 0x0020
717 #define TI_BDERR_RUNT 0x0040
718 #define TI_BDERR_TRUNC 0x0080
719 #define TI_BDERR_GIANT 0x0100
724 #define TI_BDFLAG_TCP_UDP_CKSUM 0x0001
725 #define TI_BDFLAG_IP_CKSUM 0x0002
726 #define TI_BDFLAG_END 0x0004
727 #define TI_BDFLAG_MORE 0x0008
728 #define TI_BDFLAG_JUMBO_RING 0x0010
729 #define TI_BDFLAG_UCAST_PKT 0x0020
730 #define TI_BDFLAG_MCAST_PKT 0x0040
731 #define TI_BDFLAG_BCAST_PKT 0x0060
732 #define TI_BDFLAG_IP_FRAG 0x0080
733 #define TI_BDFLAG_IP_FRAG_END 0x0100
734 #define TI_BDFLAG_VLAN_TAG 0x0200
735 #define TI_BDFLAG_ERROR 0x0400
736 #define TI_BDFLAG_COAL_NOW 0x0800
737 #define TI_BDFLAG_MINI_RING 0x1000
744 #define TI_BDTYPE_TYPE_NULL 0x0000
745 #define TI_BDTYPE_SEND_BD 0x0001
746 #define TI_BDTYPE_RECV_BD 0x0002
747 #define TI_BDTYPE_RECV_JUMBO_BD 0x0003
748 #define TI_BDTYPE_RECV_BD_LAST 0x0004
749 #define TI_BDTYPE_SEND_DATA 0x0005
750 #define TI_BDTYPE_SEND_DATA_LAST 0x0006
751 #define TI_BDTYPE_RECV_DATA 0x0007
752 #define TI_BDTYPE_RECV_DATA_LAST 0x000b
753 #define TI_BDTYPE_EVENT_RUPT 0x000c
754 #define TI_BDTYPE_EVENT_NO_RUPT 0x000d
755 #define TI_BDTYPE_ODD_START 0x000e
756 #define TI_BDTYPE_UPDATE_STATS 0x000f
757 #define TI_BDTYPE_SEND_DUMMY_DMA 0x0010
758 #define TI_BDTYPE_EVENT_PROD 0x0011
759 #define TI_BDTYPE_TX_CONS 0x0012
760 #define TI_BDTYPE_RX_PROD 0x0013
761 #define TI_BDTYPE_REFRESH_STATS 0x0014
762 #define TI_BDTYPE_SEND_DATA_LAST_VLAN 0x0015
763 #define TI_BDTYPE_SEND_DATA_COAL 0x0016
764 #define TI_BDTYPE_SEND_DATA_LAST_COAL 0x0017
765 #define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL 0x0018
766 #define TI_BDTYPE_TX_CONS_NO_INTR 0x0019
775 #define TI_CMD_CMD(cmd) (((((cmd)->ti_cmdx)) >> 24) & 0xff)
776 #define TI_CMD_CODE(cmd) (((((cmd)->ti_cmdx)) >> 12) & 0xfff)
777 #define TI_CMD_IDX(cmd) ((((cmd)->ti_cmdx)) & 0xfff)
779 #define TI_CMD_HOST_STATE 0x01
780 #define TI_CMD_CODE_STACK_UP 0x01
781 #define TI_CMD_CODE_STACK_DOWN 0x02
787 #define TI_CMD_FDR_FILTERING 0x02
788 #define TI_CMD_CODE_FILT_ENB 0x01
789 #define TI_CMD_CODE_FILT_DIS 0x02
791 #define TI_CMD_SET_RX_PROD_IDX 0x03 /* obsolete */
792 #define TI_CMD_UPDATE_GENCOM 0x04
793 #define TI_CMD_RESET_JUMBO_RING 0x05
794 #define TI_CMD_SET_PARTIAL_RX_CNT 0x06
795 #define TI_CMD_ADD_MCAST_ADDR 0x08 /* obsolete */
796 #define TI_CMD_DEL_MCAST_ADDR 0x09 /* obsolete */
798 #define TI_CMD_SET_PROMISC_MODE 0x0A
799 #define TI_CMD_CODE_PROMISC_ENB 0x01
800 #define TI_CMD_CODE_PROMISC_DIS 0x02
802 #define TI_CMD_LINK_NEGOTIATION 0x0B
803 #define TI_CMD_CODE_NEGOTIATE_BOTH 0x00
804 #define TI_CMD_CODE_NEGOTIATE_GIGABIT 0x01
805 #define TI_CMD_CODE_NEGOTIATE_10_100 0x02
807 #define TI_CMD_SET_MAC_ADDR 0x0C
808 #define TI_CMD_CLR_PROFILE 0x0D
810 #define TI_CMD_SET_ALLMULTI 0x0E
811 #define TI_CMD_CODE_ALLMULTI_ENB 0x01
812 #define TI_CMD_CODE_ALLMULTI_DIS 0x02
814 #define TI_CMD_CLR_STATS 0x0F
815 #define TI_CMD_SET_RX_JUMBO_PROD_IDX 0x10 /* obsolete */
816 #define TI_CMD_RFRSH_STATS 0x11
818 #define TI_CMD_EXT_ADD_MCAST 0x12
819 #define TI_CMD_EXT_DEL_MCAST 0x13
828 } while(0)
833 } while(0)
842 TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, (y)); \
845 } while(0)
852 TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, (y)); \
855 } while(0)
866 #define TI_EVENT_EVENT(e) (((((e)->ti_eventx)) >> 24) & 0xff)
867 #define TI_EVENT_CODE(e) (((((e)->ti_eventx)) >> 12) & 0xfff)
868 #define TI_EVENT_IDX(e) (((((e)->ti_eventx))) & 0xfff)
873 #define TI_EV_FIRMWARE_UP 0x01
874 #define TI_EV_STATS_UPDATED 0x04
876 #define TI_EV_LINKSTAT_CHANGED 0x06
877 #define TI_EV_CODE_GIG_LINK_UP 0x01
878 #define TI_EV_CODE_LINK_DOWN 0x02
879 #define TI_EV_CODE_LINK_UP 0x03
881 #define TI_EV_ERROR 0x07
882 #define TI_EV_CODE_ERR_INVAL_CMD 0x01
883 #define TI_EV_CODE_ERR_UNIMP_CMD 0x02
884 #define TI_EV_CODE_ERR_BADCFG 0x03
886 #define TI_EV_MCAST_UPDATED 0x08
887 #define TI_EV_CODE_MCAST_ADD 0x01
888 #define TI_EV_CODE_MCAST_DEL 0x02
890 #define TI_EV_RESET_JUMBO_RING 0x09
1006 #define TI_HWREV_TIGON 0x01
1007 #define TI_HWREV_TIGON_II 0x02
1009 #define TI_TXCONS_UNSET 0xFFFF /* impossible value */
1012 TI_FLAG_NONE = 0x00,
1013 TI_FLAG_DEBUGING = 0x01,
1014 TI_FLAG_WAIT_FOR_LINK = 0x02
1068 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */
1069 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */
1078 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\
1080 } while(0)
1088 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */ \
1094 } while(0)