93 	{ VENDOR_INTEL, TB_DEV_AR_2C, 0xffff, 0xffff, TB_GEN_TB3|TB_HWIF_AR,
95 	{ VENDOR_INTEL, TB_DEV_AR_LP, 0xffff, 0xffff, TB_GEN_TB3|TB_HWIF_AR,
97 	{ VENDOR_INTEL, TB_DEV_AR_C_4C, 0xffff, 0xffff, TB_GEN_TB3|TB_HWIF_AR,
99 	{ VENDOR_INTEL, TB_DEV_AR_C_2C, 0xffff, 0xffff, TB_GEN_TB3|TB_HWIF_AR,
101 	{ VENDOR_INTEL, TB_DEV_ICL_0, 0xffff, 0xffff, TB_GEN_TB3|TB_HWIF_ICL,
103 	{ VENDOR_INTEL, TB_DEV_ICL_1, 0xffff, 0xffff, TB_GEN_TB3|TB_HWIF_ICL,
105 	{ 0, 0, 0, 0, 0, NULL }
119 	for (n = tb_pcib_identifiers; n->vendor != 0; n++) {  in tb_pcib_find_ident()
122 		if (((n->subvendor != 0xffff) && (n->subvendor != sv)) ||  in tb_pcib_find_ident()
123 		    ((n->subdevice != 0xffff) && (n->subdevice != sd)))  in tb_pcib_find_ident()
137 	sc->debug = 0;  in tb_pcib_get_tunables()
141 	if (TUNABLE_STR_FETCH("hw.tbolt.debug_level", oid, 80) != 0)  in tb_pcib_get_tunables()
148 	if (TUNABLE_STR_FETCH(tmpstr, oid, 80) != 0)  in tb_pcib_get_tunables()
173 	    &sc->debug, 0, tb_debug_sysctl, "A", "Thunderbolt debug level");  in tb_pcib_setup_sysctl()
175 	return (0);  in tb_pcib_setup_sysctl()
180  * 0, doing so will force the ACPI attachment to fail.
191 		if ((TB_FIND_UFP(dev, &ufp) == 0) && (ufp == dev))  in tb_pcib_probe_common()
207 	if ((val = tb_pcib_probe_common(dev, desc)) <= 0)  in tb_pcib_probe()
245 	if ((TB_FIND_UFP(dev, &ufp) == 0) && (ufp != NULL)) {  in tb_pcib_attach_common()
276 		cmd.data_in = 0;  in tb_pcib_attach_common()
279 		tb_debug(sc, DBG_BRIDGE, "SXEXIT returned error= %d resp= 0x%x "  in tb_pcib_attach_common()
280 		    "data= 0x%x\n", error, cmd.cmd_resp, cmd.data_out);  in tb_pcib_attach_common()
287 		tb_debug(sc, DBG_BRIDGE|DBG_FULL, "VSEC+0x1c= 0x%08x\n", val);  in tb_pcib_attach_common()
292 		tb_debug(sc, DBG_BRIDGE|DBG_FULL, "VSEC+0xb0= 0x%08x\n", val);  in tb_pcib_attach_common()
297 	return (0);  in tb_pcib_attach_common()
323 	if (0 && TB_IS_ROOT(sc)) {  in tb_pcib_detach()
327 		cmd.data_in = 0;  in tb_pcib_detach()
330 		tb_debug(sc, DBG_BRIDGE, "SXEXIT returned error= %d resp= 0x%x "  in tb_pcib_detach()
331 		    "data= 0x%x\n", error, cmd.cmd_resp, cmd.data_out);  in tb_pcib_detach()
363 	tb_debug(sc, DBG_BRIDGE|DBG_FULL, "Writing LC cmd 0x%x\n", regcmd);  in tb_pcib_lc_mailbox()
366 	for (i = 0; i < 10; i++) {  in tb_pcib_lc_mailbox()
369 		tb_debug(sc, DBG_BRIDGE|DBG_FULL, "LC Mailbox= 0x%08x\n",  in tb_pcib_lc_mailbox()
371 		if ((result & LC_MBOXIN_DONE) != 0)  in tb_pcib_lc_mailbox()
376 	pci_write_config(dev, vsec + m_out, 0, 4);  in tb_pcib_lc_mailbox()
381 	if ((result & LC_MBOXIN_DONE) == 0)  in tb_pcib_lc_mailbox()
384 	return (0);  in tb_pcib_lc_mailbox()
390 #if 0  in tb_pcib_pcie2cio_wait()
397                 if ((val & PCIE2CIO_CMD_START) == 0) {  in tb_pcib_pcie2cio_wait()
400                         return 0;  in tb_pcib_pcie2cio_wait()
414 #if 0  in tb_pcib_pcie2cio_read()
428         if ((ret = pci2cio_wait_completion(dev, 5000)) != 0)  in tb_pcib_pcie2cio_read()
433 	return (0);  in tb_pcib_pcie2cio_read()
440 #if 0  in tb_pcib_pcie2cio_write()
481 		error = 0;  in tb_pcib_find_ufp()
492 	if (error == 0) {  in tb_pcib_find_ufp()
493 		val = pci_read_config(dev, vsec + 0x18, 4);  in tb_pcib_find_ufp()
494 		if ((val & 0x1f) > 0) {  in tb_pcib_find_ufp()
508 		error = 0;  in tb_pcib_find_ufp()
530 	return (0);  in tb_pcib_get_debug()