Lines Matching +full:0 +full:xffff
100 { VENDOR_INTEL, DEVICE_AR_2C_NHI, 0xffff, 0xffff, NHI_TYPE_AR,
102 { VENDOR_INTEL, DEVICE_AR_DP_B_NHI, 0xffff, 0xffff, NHI_TYPE_AR,
104 { VENDOR_INTEL, DEVICE_AR_DP_C_NHI, 0xffff, 0xffff, NHI_TYPE_AR,
106 { VENDOR_INTEL, DEVICE_AR_LP_NHI, 0xffff, 0xffff, NHI_TYPE_AR,
108 { VENDOR_INTEL, DEVICE_ICL_NHI_0, 0xffff, 0xffff, NHI_TYPE_ICL,
109 "Thunderbolt 3 NHI Port 0 (IceLake)" },
110 { VENDOR_INTEL, DEVICE_ICL_NHI_1, 0xffff, 0xffff, NHI_TYPE_ICL,
112 { VENDOR_AMD, DEVICE_PINK_SARDINE_0, 0xffff, 0xffff, NHI_TYPE_USB4,
113 "USB4 NHI Port 0 (Pink Sardine)" },
114 { VENDOR_AMD, DEVICE_PINK_SARDINE_1, 0xffff, 0xffff, NHI_TYPE_USB4,
116 { 0, 0, 0, 0, 0, NULL }
129 for (n = nhi_identifiers; n->vendor != 0; n++) { in nhi_find_ident()
134 if ((n->subvendor != 0xffff) && in nhi_find_ident()
137 if ((n->subdevice != 0xffff) && in nhi_find_ident()
151 if (resource_disabled("tb", 0)) in nhi_pci_probe()
167 int error = 0; in nhi_pci_attach()
182 if ((TB_FIND_UFP(dev, &sc->ufp) != 0) || (sc->ufp == NULL)) { in nhi_pci_attach()
194 if ((error = nhi_pci_icl_poweron(sc)) != 0) in nhi_pci_attach()
200 sc->regs_rid = PCIR_BAR(0); in nhi_pci_attach()
211 if (bus_dma_template_tag(&t, &sc->parent_dmat) != 0) { in nhi_pci_attach()
218 if (error == 0) in nhi_pci_attach()
220 if (error != 0) in nhi_pci_attach()
235 return (0); in nhi_pci_detach()
242 return (0); in nhi_pci_suspend()
249 return (0); in nhi_pci_resume()
275 int msgs, error = 0; in nhi_pci_allocate_interrupts()
293 if (msgs != 0) { in nhi_pci_allocate_interrupts()
301 if ((error != 0) || (msgs <= 0)) { in nhi_pci_allocate_interrupts()
303 msgs = 0; in nhi_pci_allocate_interrupts()
315 for (i = 0; i < sc->msix_count; i++) { in nhi_pci_free_interrupts()
355 for (i = 0; i < sc->msix_count; i++) { in nhi_pci_configure_interrupts()
383 for (i = 0; i < 16; i ++) in nhi_pci_configure_interrupts()
384 nhi_write_reg(sc, NHI_ITR0 + i * 4, 0x1f4); in nhi_pci_configure_interrupts()
395 } while (0)
410 ivr[0] = nhi_read_reg(sc, NHI_IVR0); in nhi_pci_enable_interrupt()
418 NHI_SET_INTERRUPT(offset, 0x0f, r->ring_num); in nhi_pci_enable_interrupt()
422 NHI_SET_INTERRUPT(offset, 0x0f, r->ring_num); in nhi_pci_enable_interrupt()
426 NHI_SET_INTERRUPT(offset, 0x0f, 0x0f); in nhi_pci_enable_interrupt()
428 nhi_write_reg(sc, NHI_IVR0, ivr[0]); in nhi_pci_enable_interrupt()
435 "Wrote IVR 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", in nhi_pci_enable_interrupt()
436 ivr[0], ivr[1], ivr[2], ivr[3], ivr[4]); in nhi_pci_enable_interrupt()
439 ivr[0] = nhi_read_reg(sc, NHI_IMR0); in nhi_pci_enable_interrupt()
444 NHI_SET_INTERRUPT(offset, 0x01, 1); in nhi_pci_enable_interrupt()
448 NHI_SET_INTERRUPT(offset, 0x01, 1); in nhi_pci_enable_interrupt()
452 NHI_SET_INTERRUPT(offset, 0x01, 1); in nhi_pci_enable_interrupt()
454 nhi_write_reg(sc, NHI_IMR0, ivr[0]); in nhi_pci_enable_interrupt()
457 "Wrote IMR 0x%08x 0x%08x\n", ivr[0], ivr[1]); in nhi_pci_enable_interrupt()
465 nhi_write_reg(sc, NHI_IMR0, 0); in nhi_pci_disable_interrupts()
466 nhi_write_reg(sc, NHI_IMR1, 0); in nhi_pci_disable_interrupts()
467 nhi_write_reg(sc, NHI_IVR0, 0); in nhi_pci_disable_interrupts()
468 nhi_write_reg(sc, NHI_IVR1, 0); in nhi_pci_disable_interrupts()
469 nhi_write_reg(sc, NHI_IVR2, 0); in nhi_pci_disable_interrupts()
470 nhi_write_reg(sc, NHI_IVR3, 0); in nhi_pci_disable_interrupts()
471 nhi_write_reg(sc, NHI_IVR4, 0); in nhi_pci_disable_interrupts()
486 int i, error = 0; in nhi_pci_icl_poweron()
490 tb_debug(sc, DBG_INIT, "icl_poweron val= 0x%x\n", val); in nhi_pci_icl_poweron()
492 return (0); in nhi_pci_icl_poweron()
496 tb_debug(sc, DBG_INIT|DBG_FULL, "icl_poweron writing 0x%x\n", val); in nhi_pci_icl_poweron()
500 for (i = 0; i < 15; i++) { in nhi_pci_icl_poweron()
504 error = 0; in nhi_pci_icl_poweron()
522 val[0] = pci_read_config(dev, ICL_VSCAP_10, 4); in nhi_pci_get_uuid()
524 val[2] = 0xffffffff; in nhi_pci_get_uuid()
525 val[3] = 0xffffffff; in nhi_pci_get_uuid()
528 return (0); in nhi_pci_get_uuid()