Lines Matching +full:- +full:u
3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
46 * D-Link Systems PCI vendor ID
64 * D-Link Systems device ID
77 * Note that while DMA addresses are all in 64-bit fields, only
90 bus_write_4((_sc)->sc_res[0], (reg), (val))
92 bus_write_2((_sc)->sc_res[0], (reg), (val))
94 bus_write_1((_sc)->sc_res[0], (reg), (val))
97 bus_read_4((_sc)->sc_res[0], (reg))
99 bus_read_2((_sc)->sc_res[0], (reg))
101 bus_read_1((_sc)->sc_res[0], (reg))
104 bus_barrier((_sc)->sc_res[0], reg, length, flags)
198 #define DMAC_RxDMAComplete (1U << 3)
199 #define DMAC_RxDMAPollNow (1U << 4)
200 #define DMAC_TxDMAComplete (1U << 11)
201 #define DMAC_TxDMAPollNow (1U << 12)
202 #define DMAC_TxDMAInProg (1U << 15)
203 #define DMAC_RxEarlyDisable (1U << 16)
204 #define DMAC_MWIDisable (1U << 18)
205 #define DMAC_TxWriteBackDisable (1U << 19)
207 #define DMAC_TargetAbort (1U << 30)
208 #define DMAC_MasterAbort (1U << 31)
216 #define STGE_TxDMABurstThresh 0x18 /* 8-bit */
218 #define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */
220 #define STGE_TxDMAPollPeriod 0x1a /* 8-bit, 320ns increments */
226 #define STGE_RxDMABurstThresh 0x24 /* 8-bit */
228 #define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */
230 #define STGE_RxDMAPollPeriod 0x26 /* 8-bit, 320ns increments */
252 #define STGE_DebugCtrl 0x2c /* 16-bit */
253 #define DC_GPIO0Ctrl (1U << 0)
254 #define DC_GPIO1Ctrl (1U << 1)
255 #define DC_GPIO0 (1U << 2)
256 #define DC_GPIO1 (1U << 3)
259 #define AC_ExpRomDisable (1U << 0)
260 #define AC_ExpRomSize (1U << 1)
261 #define AC_PhySpeed10 (1U << 4)
262 #define AC_PhySpeed100 (1U << 5)
263 #define AC_PhySpeed1000 (1U << 6)
264 #define AC_PhyMedia (1U << 7)
267 #define AC_D3ResetDisable (1U << 11)
268 #define AC_SpeedupMode (1U << 13)
269 #define AC_LEDMode (1U << 14)
270 #define AC_RstOutPolarity (1U << 15)
271 #define AC_GlobalReset (1U << 16)
272 #define AC_RxReset (1U << 17)
273 #define AC_TxReset (1U << 18)
274 #define AC_DMA (1U << 19)
275 #define AC_FIFO (1U << 20)
276 #define AC_Network (1U << 21)
277 #define AC_Host (1U << 22)
278 #define AC_AutoInit (1U << 23)
279 #define AC_RstOut (1U << 24)
280 #define AC_InterruptRequest (1U << 25)
281 #define AC_ResetBusy (1U << 26)
282 #define AC_LEDSpeed (1U << 27)
283 #define AC_LEDModeBit1 (1U << 29)
285 #define STGE_FIFOCtrl 0x38 /* 16-bit */
286 #define FC_RAMTestMode (1U << 0)
287 #define FC_Transmitting (1U << 14)
288 #define FC_Receiving (1U << 15)
290 #define STGE_RxEarlyThresh 0x3a /* 16-bit */
292 #define STGE_FlowOffThresh 0x3c /* 16-bit */
294 #define STGE_FlowOnTresh 0x3e /* 16-bit */
296 #define STGE_TxStartThresh 0x44 /* 16-bit */
298 #define STGE_EepromData 0x48 /* 16-bit */
300 #define STGE_EepromCtrl 0x4a /* 16-bit */
307 #define EC_EepromBusy (1U << 15)
311 #define STGE_ExpRomData 0x50 /* 8-bit */
313 #define STGE_WakeEvent 0x51 /* 8-bit */
314 #define WE_WakePktEnable (1U << 0)
315 #define WE_MagicPktEnable (1U << 1)
316 #define WE_LinkEventEnable (1U << 2)
317 #define WE_WakePolarity (1U << 3)
318 #define WE_WakePktEvent (1U << 4)
319 #define WE_MagicPktEvent (1U << 5)
320 #define WE_LinkEvent (1U << 6)
321 #define WE_WakeOnLanEnable (1U << 7)
325 #define CD_CountdownSpeed (1U << 24)
326 #define CD_CountdownMode (1U << 25)
327 #define CD_CountdownIntEnabled (1U << 26)
329 #define STGE_IntStatusAck 0x5a /* 16-bit */
331 #define STGE_IntEnable 0x5c /* 16-bit */
333 #define STGE_IntStatus 0x5e /* 16-bit */
335 #define IS_InterruptStatus (1U << 0)
336 #define IS_HostError (1U << 1)
337 #define IS_TxComplete (1U << 2)
338 #define IS_MACControlFrame (1U << 3)
339 #define IS_RxComplete (1U << 4)
340 #define IS_RxEarly (1U << 5)
341 #define IS_InRequested (1U << 6)
342 #define IS_UpdateStats (1U << 7)
343 #define IS_LinkEvent (1U << 8)
344 #define IS_TxDMAComplete (1U << 9)
345 #define IS_RxDMAComplete (1U << 10)
346 #define IS_RFDListEnd (1U << 11)
347 #define IS_RxDMAPriority (1U << 12)
350 #define TS_TxError (1U << 0)
351 #define TS_LateCollision (1U << 2)
352 #define TS_MaxCollisions (1U << 3)
353 #define TS_TxUnderrun (1U << 4)
354 #define TS_TxIndicateReqd (1U << 6)
355 #define TS_TxComplete (1U << 7)
365 #define MC_DuplexSelect (1U << 5)
366 #define MC_RcvLargeFrames (1U << 6)
367 #define MC_TxFlowControlEnable (1U << 7)
368 #define MC_RxFlowControlEnable (1U << 8)
369 #define MC_RcvFCS (1U << 9)
370 #define MC_FIFOLoopback (1U << 10)
371 #define MC_MACLoopback (1U << 11)
372 #define MC_AutoVLANtagging (1U << 12)
373 #define MC_AutoVLANuntagging (1U << 13)
374 #define MC_CollisionDetect (1U << 16)
375 #define MC_CarrierSense (1U << 17)
376 #define MC_StatisticsEnable (1U << 21)
377 #define MC_StatisticsDisable (1U << 22)
378 #define MC_StatisticsEnabled (1U << 23)
379 #define MC_TxEnable (1U << 24)
380 #define MC_TxDisable (1U << 25)
381 #define MC_TxEnabled (1U << 26)
382 #define MC_RxEnable (1U << 27)
383 #define MC_RxDisable (1U << 28)
384 #define MC_RxEnabled (1U << 29)
385 #define MC_Paused (1U << 30)
390 #define STGE_PhySet 0x75 /* 8-bit */
391 #define PS_MemLenb9b (1U << 0)
392 #define PS_MemLen (1U << 1)
393 #define PS_NonCompdet (1U << 2)
395 #define STGE_PhyCtrl 0x76 /* 8-bit */
396 #define PC_MgmtClk (1U << 0)
397 #define PC_MgmtData (1U << 1)
398 #define PC_MgmtDir (1U << 2) /* MAC->PHY */
399 #define PC_PhyDuplexPolarity (1U << 3)
400 #define PC_PhyDuplexStatus (1U << 4)
401 #define PC_PhyLnkPolarity (1U << 5)
408 #define STGE_StationAddress0 0x78 /* 16-bit */
410 #define STGE_StationAddress1 0x7a /* 16-bit */
412 #define STGE_StationAddress2 0x7c /* 16-bit */
414 #define STGE_VLANHashTable 0x7e /* 16-bit */
420 #define STGE_ReceiveMode 0x88 /* 16-bit */
421 #define RM_ReceiveUnicast (1U << 0)
422 #define RM_ReceiveMulticast (1U << 1)
423 #define RM_ReceiveBroadcast (1U << 2)
424 #define RM_ReceiveAllFrames (1U << 3)
425 #define RM_ReceiveMulticastHash (1U << 4)
426 #define RM_ReceiveIPMulticast (1U << 5)
427 #define RM_ReceiveVLANMatch (1U << 8)
428 #define RM_ReceiveVLANHash (1U << 9)
438 #define STGE_RxJumboFrames 0xbc /* 16-bit */
440 #define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */
442 #define STGE_IPCheckSumErrors 0xc2 /* 16-bit */
444 #define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */
446 #define STGE_TxJumboFrames 0xf4 /* 16-bit */
462 #define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */
464 #define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */
466 #define STGE_FrameTooLongErrors 0xc8 /* 16-bit */
468 #define STGE_InRangeLengthErrors 0xca /* 16-bit */
470 #define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */
472 #define STGE_FramesLostRxErrors 0xce /* 16-bit */
492 #define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */
494 #define STGE_CarrierSenseErrors 0xf8 /* 16-bit */
496 #define STGE_MacControlFramesXmtd 0xfa /* 16-bit */
498 #define STGE_FramesAbortXSColls 0xfc /* 16-bit */
500 #define STGE_FramesWEXDeferal 0xfe /* 16-bit */
503 * RMON-compatible statistics. Only accessible if memory-mapped.
553 #define STGE_TX_HIWAT (STGE_TX_RING_CNT - STGE_TX_LOWAT)
564 (STGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
618 ((sc)->sc_rdata.stge_tx_ring_paddr + sizeof(struct stge_tfd) * (i))
620 ((sc)->sc_rdata.stge_rx_ring_paddr + sizeof(struct stge_rfd) * (i))
667 #define STGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
668 #define STGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
669 #define STGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
670 #define STGE_MII_LOCK(_sc) mtx_lock(&(_sc)->sc_mii_mtx)
671 #define STGE_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mii_mtx)
677 (_sc)->sc_cdata.stge_rxhead = NULL; \
678 (_sc)->sc_cdata.stge_rxtail = NULL; \
679 (_sc)->sc_cdata.stge_rxlen = 0; \