Lines Matching +full:tx +full:- +full:burst +full:- +full:length

1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
18  * 4. Neither the name of the author nor the names of any co-contributors
44  * D-Link PCI device/vendor ID for the DL10050[AB] chip
53  * There are 32-bit, 16-bit and 8-bit registers.
136  * TX DMA burst thresh is the number of 32-byte blocks that
137  * must be loaded into the TX Fifo before a TXDMA burst request
143  * The number of 32-byte blocks in the TX FIFO falls below the
144  * TX DMA urgent threshold, a TX DMA urgent request will be
167  * RX DMA burst thresh is the number of 32-byte blocks that
174  * The number of 32-byte blocks in the RX FIFO falls below the
231  * The number of bytes that must in present in the TX FIFO before
305  * only one 32-bit MACCTL register. In fact, there are two
306  * 16-bit registers side by side, and you have to access them
429  * A TFD is 16 to 512 bytes in length which means it can have up to 126
430  * fragments for a single Tx frame. Since most frames used in stack have
431  * 3-4 fragments supporting 8 fragments would be enough for normal
482 	bus_write_4((sc)->ste_res, reg, val)
484 	bus_write_2((sc)->ste_res, reg, val)
486 	bus_write_1((sc)->ste_res, reg, val)
489 	bus_read_4((sc)->ste_res, reg)
491 	bus_read_2((sc)->ste_res, reg)
493 	bus_read_1((sc)->ste_res, reg)
495 #define	CSR_BARRIER(sc, reg, length, flags)				\  argument
496 	bus_barrier((sc)->ste_res, reg, length, flags)
509  * Since Tx status can hold up to 31 status bytes we should
510  * check Tx status before controller fills it up. Otherwise
511  * Tx MAC stalls.
519 #define STE_DEC(x, y)		(x) = ((x) + ((y) - 1)) % (y)
593 #define	STE_LOCK(_sc)		mtx_lock(&(_sc)->ste_mtx)
594 #define	STE_UNLOCK(_sc)		mtx_unlock(&(_sc)->ste_mtx)
595 #define	STE_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->ste_mtx, MA_OWNED)