Lines Matching refs:m3_wr_2
274 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data) macro
288 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); in m3_rd_assp()
289 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); in m3_rd_assp()
297 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); in m3_wr_assp()
298 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); in m3_wr_assp()
299 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data); in m3_wr_assp()
361 m3_wr_2(sc, CODEC_DATA, data); in m3_wrcd()
666 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); in m3_pchan_trigger_locked()
688 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); in m3_pchan_trigger_locked()
1022 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); in m3_rchan_trigger_locked()
1041 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); in m3_rchan_trigger_locked()
1526 m3_wr_2(sc, HOST_INT_CTRL, 0); in m3_pci_suspend()
1693 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE); in m3_enable_ints()
1721 m3_wr_2(sc, GPIO_MASK, ~gpo); in m3_amp_enable()
1723 m3_wr_2(sc, GPIO_DIRECTION, data | gpo); in m3_amp_enable()
1725 m3_wr_2(sc, GPIO_DATA, data); in m3_amp_enable()
1726 m3_wr_2(sc, GPIO_MASK, ~0); in m3_amp_enable()
1742 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK); in m3_codec_reset()
1744 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT); in m3_codec_reset()
1746 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN); in m3_codec_reset()
1748 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE); in m3_codec_reset()
1751 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97); in m3_codec_reset()
1752 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97); in m3_codec_reset()
1753 m3_wr_2(sc, GPIO_DATA, 0); in m3_codec_reset()
1754 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97); in m3_codec_reset()
1756 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97); in m3_codec_reset()
1758 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE | in m3_codec_reset()
1760 m3_wr_2(sc, GPIO_MASK, ~0); in m3_codec_reset()