162 	uint32_t regbase, spdreg;  member
324 	int i, cr, regbase;  in ich_resetchan()  local
327 		regbase = ICH_REG_PO_BASE;  in ich_resetchan()
329 		regbase = ICH_REG_PI_BASE;  in ich_resetchan()
331 		regbase = ICH_REG_MC_BASE;  in ich_resetchan()
335 	ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1);  in ich_resetchan()
340 	(void)ich_rd(sc, regbase + ICH_REG_X_CR, 1);  in ich_resetchan()
342 	ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);  in ich_resetchan()
344 		cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1);  in ich_resetchan()
391 		ch->regbase = ICH_REG_PO_BASE;  in ichchan_init()
398 		ch->regbase = ICH_REG_PI_BASE;  in ichchan_init()
405 		ch->regbase = ICH_REG_MC_BASE;  in ichchan_init()
424 	ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);  in ichchan_init()
502 	ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);  in ichchan_setblocksize()
525 		ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);  in ichchan_trigger()
526 		ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);  in ichchan_trigger()
557 	ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;  in ichchan_getptr()
626 		st = ich_rd(sc, ch->regbase +  in ich_intr()
637 			lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);  in ich_intr()
649 			ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1);  in ich_intr()
652 		ich_wr(sc, ch->regbase +  in ich_intr()
731 	KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction"));  in ich_calibrate()
754 	ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);  in ich_calibrate()
756 	ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);  in ich_calibrate()
760 	ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1);  in ich_calibrate()
767 		nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);  in ich_calibrate()
771 	ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1);  in ich_calibrate()
775 	ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);  in ich_calibrate()