Lines Matching +full:ati +full:- +full:mode
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
54 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
55 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
56 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
80 { HDA_INTEL_CMLKLP, "Intel Comet Lake-LP", 0, 0 },
81 { HDA_INTEL_CMLKH, "Intel Comet Lake-H", 0, 0 },
88 { HDA_INTEL_BXTNT, "Intel Broxton-T", 0, 0 },
98 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 },
99 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 },
100 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 },
101 { HDA_INTEL_KBLKLP, "Intel Kaby Lake-LP", 0, 0 },
104 { HDA_INTEL_KBLKH, "Intel Kaby Lake-H", 0, 0 },
106 { HDA_INTEL_CMLKS, "Intel Comet Lake-S", 0, 0 },
110 { HDA_INTEL_TGLKH, "Intel Tiger Lake-H", 0, 0 },
113 { HDA_INTEL_ALLKM, "Intel Alder Lake-M", 0, 0 },
114 { HDA_INTEL_ALLKN, "Intel Alder Lake-N", 0, 0 },
115 { HDA_INTEL_ALLKP1, "Intel Alder Lake-P", 0, 0 },
116 { HDA_INTEL_ALLKP2, "Intel Alder Lake-P", 0, 0 },
117 { HDA_INTEL_ALLKPS, "Intel Alder Lake-PS", 0, 0 },
118 { HDA_INTEL_RPTLK1, "Intel Raptor Lake-P", 0, 0 },
119 { HDA_INTEL_RPTLK2, "Intel Raptor Lake-P", 0, 0 },
120 { HDA_INTEL_MTL, "Intel Meteor Lake-P", 0, 0 },
121 { HDA_INTEL_ARLS, "Intel Arrow Lake-S", 0, 0 },
123 { HDA_INTEL_LNLP, "Intel Lunar Lake-P", 0, 0 },
136 { HDA_INTEL_BXTNP, "Intel Broxton-P", 0, 0 },
171 { HDA_ATI_SB450, "ATI SB450", 0, 0 },
172 { HDA_ATI_SB600, "ATI SB600", 0, 0 },
173 { HDA_ATI_RS600, "ATI RS600", 0, 0 },
174 { HDA_ATI_RS690, "ATI RS690", 0, 0 },
175 { HDA_ATI_RS780, "ATI RS780", 0, 0 },
176 { HDA_ATI_RS880, "ATI RS880", 0, 0 },
177 { HDA_ATI_R600, "ATI R600", 0, 0 },
178 { HDA_ATI_RV610, "ATI RV610", 0, 0 },
179 { HDA_ATI_RV620, "ATI RV620", 0, 0 },
180 { HDA_ATI_RV630, "ATI RV630", 0, 0 },
181 { HDA_ATI_RV635, "ATI RV635", 0, 0 },
182 { HDA_ATI_RV710, "ATI RV710", 0, 0 },
183 { HDA_ATI_RV730, "ATI RV730", 0, 0 },
184 { HDA_ATI_RV740, "ATI RV740", 0, 0 },
185 { HDA_ATI_RV770, "ATI RV770", 0, 0 },
186 { HDA_ATI_RV810, "ATI RV810", 0, 0 },
187 { HDA_ATI_RV830, "ATI RV830", 0, 0 },
188 { HDA_ATI_RV840, "ATI RV840", 0, 0 },
189 { HDA_ATI_RV870, "ATI RV870", 0, 0 },
190 { HDA_ATI_RV910, "ATI RV910", 0, 0 },
191 { HDA_ATI_RV930, "ATI RV930", 0, 0 },
192 { HDA_ATI_RV940, "ATI RV940", 0, 0 },
193 { HDA_ATI_RV970, "ATI RV970", 0, 0 },
194 { HDA_ATI_R1000, "ATI R1000", 0, 0 },
195 { HDA_ATI_OLAND, "ATI Oland", 0, 0 },
196 { HDA_ATI_KABINI, "ATI Kabini", 0, 0 },
197 { HDA_ATI_TRINITY, "ATI Trinity", 0, 0 },
202 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 },
212 { HDA_ATI_ALL, "ATI", 0, 0 },
272 if (resource_string_value(device_get_name(sc->dev), in hdac_config_fetch()
273 device_get_unit(sc->dev), "config", &res) != 0) in hdac_config_fetch()
278 device_printf(sc->dev, "Config options:"); in hdac_config_fetch()
294 len = j - i; in hdac_config_fetch()
301 hdac_quirks_tab[k].key, len - inv) != 0) in hdac_config_fetch()
303 if (len - inv != strlen(hdac_quirks_tab[k].key)) in hdac_config_fetch()
335 * a reset or a wake-up event. in hdac_one_intr()
351 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); in hdac_one_intr()
353 HDAC_WRITE_1(&sc->mem, in hdac_one_intr()
356 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); in hdac_one_intr()
358 if (sc->unsolq_rp != sc->unsolq_wp) in hdac_one_intr()
359 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); in hdac_one_intr()
363 for (i = 0; i < sc->num_ss; i++) { in hdac_one_intr()
366 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, in hdac_one_intr()
368 if ((dev = sc->streams[i].dev) != NULL) { in hdac_one_intr()
370 sc->streams[i].dir, sc->streams[i].stream); in hdac_one_intr()
392 * from zero to one. GIS is formed by OR-ing multiple hardware in hdac_intr_handler()
396 * re-examine GIS then we can leave it set and never get an interrupt in hdac_intr_handler()
400 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); in hdac_intr_handler()
403 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); in hdac_intr_handler()
417 if (sc->polling == 0) { in hdac_poll_callback()
421 callout_reset(&sc->poll_callout, sc->poll_ival, hdac_poll_callback, sc); in hdac_poll_callback()
441 for (i = 0; i < sc->num_iss; i++) in hdac_reset()
442 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); in hdac_reset()
443 for (i = 0; i < sc->num_oss; i++) in hdac_reset()
444 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); in hdac_reset()
445 for (i = 0; i < sc->num_bss; i++) in hdac_reset()
446 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); in hdac_reset()
451 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); in hdac_reset()
452 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); in hdac_reset()
457 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); in hdac_reset()
458 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); in hdac_reset()
464 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); in hdac_reset()
465 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); in hdac_reset()
468 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); in hdac_reset()
472 } while (--count); in hdac_reset()
474 device_printf(sc->dev, "Unable to put hdac in reset\n"); in hdac_reset()
478 /* If wakeup is not requested - leave the controller in reset state. */ in hdac_reset()
483 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); in hdac_reset()
484 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); in hdac_reset()
487 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); in hdac_reset()
491 } while (--count); in hdac_reset()
493 device_printf(sc->dev, "Device stuck in reset\n"); in hdac_reset()
522 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); in hdac_get_capabilities()
523 sc->num_iss = HDAC_GCAP_ISS(gcap); in hdac_get_capabilities()
524 sc->num_oss = HDAC_GCAP_OSS(gcap); in hdac_get_capabilities()
525 sc->num_bss = HDAC_GCAP_BSS(gcap); in hdac_get_capabilities()
526 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; in hdac_get_capabilities()
527 sc->num_sdo = HDAC_GCAP_NSDO(gcap); in hdac_get_capabilities()
528 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; in hdac_get_capabilities()
529 if (sc->quirks_on & HDAC_QUIRK_64BIT) in hdac_get_capabilities()
530 sc->support_64bit = 1; in hdac_get_capabilities()
531 else if (sc->quirks_off & HDAC_QUIRK_64BIT) in hdac_get_capabilities()
532 sc->support_64bit = 0; in hdac_get_capabilities()
534 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); in hdac_get_capabilities()
537 sc->corb_size = 256; in hdac_get_capabilities()
540 sc->corb_size = 16; in hdac_get_capabilities()
543 sc->corb_size = 2; in hdac_get_capabilities()
545 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", in hdac_get_capabilities()
550 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); in hdac_get_capabilities()
553 sc->rirb_size = 256; in hdac_get_capabilities()
556 sc->rirb_size = 16; in hdac_get_capabilities()
559 sc->rirb_size = 2; in hdac_get_capabilities()
561 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", in hdac_get_capabilities()
567 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " in hdac_get_capabilities()
569 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, in hdac_get_capabilities()
570 sc->support_64bit ? ", 64bit" : "", in hdac_get_capabilities()
571 sc->corb_size, sc->rirb_size); in hdac_get_capabilities()
591 dma->dma_paddr = segs[0].ds_addr; in hdac_dma_cb()
614 bus_get_dma_tag(sc->dev), /* parent */ in hdac_dma_alloc()
617 (sc->support_64bit) ? BUS_SPACE_MAXADDR : in hdac_dma_alloc()
628 &dma->dma_tag); /* dmat */ in hdac_dma_alloc()
630 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%d)\n", in hdac_dma_alloc()
638 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, in hdac_dma_alloc()
640 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : in hdac_dma_alloc()
642 &dma->dma_map); in hdac_dma_alloc()
644 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%d)\n", in hdac_dma_alloc()
649 dma->dma_size = roundsz; in hdac_dma_alloc()
654 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, in hdac_dma_alloc()
655 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); in hdac_dma_alloc()
656 if (result != 0 || dma->dma_paddr == 0) { in hdac_dma_alloc()
659 device_printf(sc->dev, "%s: bus_dmamem_load failed (%d)\n", in hdac_dma_alloc()
665 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", in hdac_dma_alloc()
686 if (dma->dma_paddr != 0) { in hdac_dma_free()
688 bus_dmamap_sync(dma->dma_tag, dma->dma_map, in hdac_dma_free()
690 bus_dmamap_unload(dma->dma_tag, dma->dma_map); in hdac_dma_free()
691 dma->dma_paddr = 0; in hdac_dma_free()
693 if (dma->dma_vaddr != NULL) { in hdac_dma_free()
694 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); in hdac_dma_free()
695 dma->dma_vaddr = NULL; in hdac_dma_free()
697 if (dma->dma_tag != NULL) { in hdac_dma_free()
698 bus_dma_tag_destroy(dma->dma_tag); in hdac_dma_free()
699 dma->dma_tag = NULL; in hdac_dma_free()
701 dma->dma_size = 0; in hdac_dma_free()
715 mem = &sc->mem; in hdac_mem_alloc()
716 mem->mem_rid = PCIR_BAR(0); in hdac_mem_alloc()
717 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, in hdac_mem_alloc()
718 &mem->mem_rid, RF_ACTIVE); in hdac_mem_alloc()
719 if (mem->mem_res == NULL) { in hdac_mem_alloc()
720 device_printf(sc->dev, in hdac_mem_alloc()
724 mem->mem_tag = rman_get_bustag(mem->mem_res); in hdac_mem_alloc()
725 mem->mem_handle = rman_get_bushandle(mem->mem_res); in hdac_mem_alloc()
740 mem = &sc->mem; in hdac_mem_free()
741 if (mem->mem_res != NULL) in hdac_mem_free()
742 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, in hdac_mem_free()
743 mem->mem_res); in hdac_mem_free()
744 mem->mem_res = NULL; in hdac_mem_free()
758 irq = &sc->irq; in hdac_irq_alloc()
759 irq->irq_rid = 0x0; in hdac_irq_alloc()
761 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && in hdac_irq_alloc()
762 (result = pci_msi_count(sc->dev)) == 1 && in hdac_irq_alloc()
763 pci_alloc_msi(sc->dev, &result) == 0) in hdac_irq_alloc()
764 irq->irq_rid = 0x1; in hdac_irq_alloc()
766 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, in hdac_irq_alloc()
767 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); in hdac_irq_alloc()
768 if (irq->irq_res == NULL) { in hdac_irq_alloc()
769 device_printf(sc->dev, "%s: Unable to allocate irq\n", in hdac_irq_alloc()
773 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, in hdac_irq_alloc()
774 NULL, hdac_intr_handler, sc, &irq->irq_handle); in hdac_irq_alloc()
776 device_printf(sc->dev, in hdac_irq_alloc()
800 irq = &sc->irq; in hdac_irq_free()
801 if (irq->irq_res != NULL && irq->irq_handle != NULL) in hdac_irq_free()
802 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); in hdac_irq_free()
803 if (irq->irq_res != NULL) in hdac_irq_free()
804 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, in hdac_irq_free()
805 irq->irq_res); in hdac_irq_free()
806 if (irq->irq_rid == 0x1) in hdac_irq_free()
807 pci_release_msi(sc->dev); in hdac_irq_free()
808 irq->irq_handle = NULL; in hdac_irq_free()
809 irq->irq_res = NULL; in hdac_irq_free()
810 irq->irq_rid = 0x0; in hdac_irq_free()
826 switch (sc->corb_size) { in hdac_corb_init()
837 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); in hdac_corb_init()
839 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); in hdac_corb_init()
842 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; in hdac_corb_init()
843 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); in hdac_corb_init()
844 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); in hdac_corb_init()
847 sc->corb_wp = 0; in hdac_corb_init()
848 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); in hdac_corb_init()
849 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); in hdac_corb_init()
856 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); in hdac_corb_init()
860 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); in hdac_corb_init()
877 switch (sc->rirb_size) { in hdac_rirb_init()
888 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); in hdac_rirb_init()
890 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); in hdac_rirb_init()
893 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; in hdac_rirb_init()
894 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); in hdac_rirb_init()
895 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); in hdac_rirb_init()
898 sc->rirb_rp = 0; in hdac_rirb_init()
899 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); in hdac_rirb_init()
902 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); in hdac_rirb_init()
906 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, in hdac_rirb_init()
909 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); in hdac_rirb_init()
916 * read-only from now on. in hdac_rirb_init()
918 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, in hdac_rirb_init()
932 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); in hdac_corb_start()
934 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); in hdac_corb_start()
947 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); in hdac_rirb_start()
949 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); in hdac_rirb_start()
961 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; in hdac_rirb_flush()
962 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); in hdac_rirb_flush()
963 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, in hdac_rirb_flush()
967 while (sc->rirb_rp != rirbwp) { in hdac_rirb_flush()
968 sc->rirb_rp++; in hdac_rirb_flush()
969 sc->rirb_rp %= sc->rirb_size; in hdac_rirb_flush()
970 rirb = &rirb_base[sc->rirb_rp]; in hdac_rirb_flush()
971 resp = le32toh(rirb->response); in hdac_rirb_flush()
972 resp_ex = le32toh(rirb->response_ex); in hdac_rirb_flush()
975 sc->unsolq[sc->unsolq_wp++] = resp; in hdac_rirb_flush()
976 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; in hdac_rirb_flush()
977 sc->unsolq[sc->unsolq_wp++] = cad; in hdac_rirb_flush()
978 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; in hdac_rirb_flush()
979 } else if (sc->codecs[cad].pending <= 0) { in hdac_rirb_flush()
980 device_printf(sc->dev, "Unexpected unsolicited " in hdac_rirb_flush()
983 sc->codecs[cad].response = resp; in hdac_rirb_flush()
984 sc->codecs[cad].pending--; in hdac_rirb_flush()
989 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, in hdac_rirb_flush()
1002 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { in hdac_unsolq_flush()
1003 sc->unsolq_st = HDAC_UNSOLQ_BUSY; in hdac_unsolq_flush()
1004 while (sc->unsolq_rp != sc->unsolq_wp) { in hdac_unsolq_flush()
1005 resp = sc->unsolq[sc->unsolq_rp++]; in hdac_unsolq_flush()
1006 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; in hdac_unsolq_flush()
1007 cad = sc->unsolq[sc->unsolq_rp++]; in hdac_unsolq_flush()
1008 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; in hdac_unsolq_flush()
1009 if ((child = sc->codecs[cad].dev) != NULL && in hdac_unsolq_flush()
1014 sc->unsolq_st = HDAC_UNSOLQ_READY; in hdac_unsolq_flush()
1034 sc->codecs[cad].response = HDA_INVALID; in hdac_send_command()
1036 sc->codecs[cad].pending++; in hdac_send_command()
1037 sc->corb_wp++; in hdac_send_command()
1038 sc->corb_wp %= sc->corb_size; in hdac_send_command()
1039 corb = (uint32_t *)sc->corb_dma.dma_vaddr; in hdac_send_command()
1040 bus_dmamap_sync(sc->corb_dma.dma_tag, in hdac_send_command()
1041 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); in hdac_send_command()
1042 corb[sc->corb_wp] = htole32(verb); in hdac_send_command()
1043 bus_dmamap_sync(sc->corb_dma.dma_tag, in hdac_send_command()
1044 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); in hdac_send_command()
1045 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); in hdac_send_command()
1051 } while (sc->codecs[cad].pending != 0 && --timeout); in hdac_send_command()
1053 if (sc->codecs[cad].pending != 0) { in hdac_send_command()
1054 device_printf(sc->dev, "Command 0x%08x timeout on address %d\n", in hdac_send_command()
1056 sc->codecs[cad].pending = 0; in hdac_send_command()
1059 if (sc->unsolq_rp != sc->unsolq_wp) in hdac_send_command()
1060 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); in hdac_send_command()
1061 return (sc->codecs[cad].response); in hdac_send_command()
1139 int i, devid = -1; in hdac_attach()
1171 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); in hdac_attach()
1172 sc->dev = dev; in hdac_attach()
1173 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); in hdac_attach()
1174 callout_init(&sc->poll_callout, 1); in hdac_attach()
1176 sc->codecs[i].dev = NULL; in hdac_attach()
1178 sc->quirks_on = hdac_devices[devid].quirks_on; in hdac_attach()
1179 sc->quirks_off = hdac_devices[devid].quirks_off; in hdac_attach()
1181 sc->quirks_on = 0; in hdac_attach()
1182 sc->quirks_off = 0; in hdac_attach()
1187 sc->quirks_off |= HDAC_QUIRK_MSI; in hdac_attach()
1189 sc->quirks_on |= HDAC_QUIRK_MSI; in hdac_attach()
1190 sc->quirks_off |= ~HDAC_QUIRK_MSI; in hdac_attach()
1193 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); in hdac_attach()
1195 device_printf(sc->dev, in hdac_attach()
1197 sc->quirks_on, sc->quirks_off); in hdac_attach()
1199 sc->poll_ival = hz; in hdac_attach()
1202 sc->polling = 1; in hdac_attach()
1204 sc->polling = 0; in hdac_attach()
1210 /* TCSEL -> TC0 */ in hdac_attach()
1214 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, in hdac_attach()
1220 sc->flags |= HDAC_F_DMA_NOCACHE; in hdac_attach()
1225 sc->flags &= ~HDAC_F_DMA_NOCACHE; in hdac_attach()
1235 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx in hdac_attach()
1240 sc->flags &= ~HDAC_F_DMA_NOCACHE; in hdac_attach()
1259 sc->flags |= HDAC_F_DMA_NOCACHE; in hdac_attach()
1270 (sc->flags & HDAC_F_DMA_NOCACHE) ? in hdac_attach()
1285 result = hdac_dma_alloc(sc, &sc->corb_dma, in hdac_attach()
1286 sc->corb_size * sizeof(uint32_t)); in hdac_attach()
1289 result = hdac_dma_alloc(sc, &sc->rirb_dma, in hdac_attach()
1290 sc->rirb_size * sizeof(struct hdac_rirb)); in hdac_attach()
1293 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss, in hdac_attach()
1295 for (i = 0; i < sc->num_ss; i++) { in hdac_attach()
1296 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, in hdac_attach()
1301 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { in hdac_attach()
1302 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { in hdac_attach()
1306 "(non-fatal)\n"); in hdac_attach()
1309 uint64_t addr = sc->pos_dma.dma_paddr; in hdac_attach()
1311 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); in hdac_attach()
1312 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, in hdac_attach()
1319 bus_get_dma_tag(sc->dev), /* parent */ in hdac_attach()
1322 (sc->support_64bit) ? BUS_SPACE_MAXADDR : in hdac_attach()
1333 &sc->chan_dmat); /* dmat */ in hdac_attach()
1355 sc->intrhook.ich_func = hdac_attach2; in hdac_attach()
1356 sc->intrhook.ich_arg = (void *)sc; in hdac_attach()
1357 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { in hdac_attach()
1358 sc->intrhook.ich_func = NULL; in hdac_attach()
1366 if (sc->streams != NULL) in hdac_attach()
1367 for (i = 0; i < sc->num_ss; i++) in hdac_attach()
1368 hdac_dma_free(sc, &sc->streams[i].bdl); in hdac_attach()
1369 free(sc->streams, M_HDAC); in hdac_attach()
1370 hdac_dma_free(sc, &sc->rirb_dma); in hdac_attach()
1371 hdac_dma_free(sc, &sc->corb_dma); in hdac_attach()
1373 snd_mtxfree(sc->lock); in hdac_attach()
1386 dev = oidp->oid_arg1; in sysctl_hdac_pindump()
1392 if (err != 0 || req->newptr == NULL || val == 0) in sysctl_hdac_pindump()
1460 if (sc->polling == 0) in hdac_poll_reinit()
1462 if (sc->unsol_registered > 0) in hdac_poll_reinit()
1464 for (i = 0; i < sc->num_ss; i++) { in hdac_poll_reinit()
1465 s = &sc->streams[i]; in hdac_poll_reinit()
1466 if (s->running == 0) in hdac_poll_reinit()
1468 pollticks = ((uint64_t)hz * s->blksz) / in hdac_poll_reinit()
1469 (hdac_mdata_rate(s->format) / 8); in hdac_poll_reinit()
1478 sc->poll_ival = min; in hdac_poll_reinit()
1480 callout_stop(&sc->poll_callout); in hdac_poll_reinit()
1482 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); in hdac_poll_reinit()
1493 dev = oidp->oid_arg1; in sysctl_hdac_polling()
1498 val = sc->polling; in sysctl_hdac_polling()
1502 if (err != 0 || req->newptr == NULL) in sysctl_hdac_polling()
1508 if (val != sc->polling) { in sysctl_hdac_polling()
1510 callout_stop(&sc->poll_callout); in sysctl_hdac_polling()
1512 callout_drain(&sc->poll_callout); in sysctl_hdac_polling()
1514 sc->polling = 0; in sysctl_hdac_polling()
1515 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); in sysctl_hdac_polling()
1517 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); in sysctl_hdac_polling()
1519 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); in sysctl_hdac_polling()
1521 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); in sysctl_hdac_polling()
1522 sc->polling = 1; in sysctl_hdac_polling()
1545 if (sc->intrhook.ich_func != NULL) { in hdac_attach2()
1546 config_intrhook_disestablish(&sc->intrhook); in hdac_attach2()
1547 sc->intrhook.ich_func = NULL; in hdac_attach2()
1551 device_printf(sc->dev, "Starting CORB Engine...\n"); in hdac_attach2()
1555 device_printf(sc->dev, "Starting RIRB Engine...\n"); in hdac_attach2()
1567 HDAC_WRITE_2(&sc->mem, HDAC_WAKEEN, 0); in hdac_attach2()
1570 * Read and clear post-reset SDI wake status. in hdac_attach2()
1573 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); in hdac_attach2()
1574 HDAC_WRITE_2(&sc->mem, HDAC_STATESTS, statests); in hdac_attach2()
1577 device_printf(sc->dev, in hdac_attach2()
1580 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | in hdac_attach2()
1582 if (sc->polling == 0) { in hdac_attach2()
1583 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, in hdac_attach2()
1589 device_printf(sc->dev, "Scanning HDA codecs ...\n"); in hdac_attach2()
1595 device_printf(sc->dev, in hdac_attach2()
1606 device_printf(sc->dev, in hdac_attach2()
1610 sc->codecs[i].vendor_id = in hdac_attach2()
1612 sc->codecs[i].device_id = in hdac_attach2()
1614 sc->codecs[i].revision_id = in hdac_attach2()
1616 sc->codecs[i].stepping_id = in hdac_attach2()
1618 child = device_add_child(sc->dev, "hdacc", DEVICE_UNIT_ANY); in hdac_attach2()
1620 device_printf(sc->dev, in hdac_attach2()
1625 sc->codecs[i].dev = child; in hdac_attach2()
1628 bus_generic_attach(sc->dev); in hdac_attach2()
1630 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), in hdac_attach2()
1631 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, in hdac_attach2()
1632 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, in hdac_attach2()
1633 sizeof(sc->dev), sysctl_hdac_pindump, "I", "Dump pin states/data"); in hdac_attach2()
1634 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), in hdac_attach2()
1635 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, in hdac_attach2()
1636 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, in hdac_attach2()
1637 sizeof(sc->dev), sysctl_hdac_polling, "I", "Enable polling mode"); in hdac_attach2()
1659 callout_stop(&sc->poll_callout); in hdac_suspend()
1662 callout_drain(&sc->poll_callout); in hdac_suspend()
1663 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); in hdac_suspend()
1714 HDAC_WRITE_2(&sc->mem, HDAC_WAKEEN, 0); in hdac_resume()
1715 HDAC_WRITE_2(&sc->mem, HDAC_STATESTS, HDAC_STATESTS_SDIWAKE_MASK); in hdac_resume()
1720 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | in hdac_resume()
1722 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); in hdac_resume()
1754 sc->codecs[cad].dev = NULL; in hdac_detach()
1761 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); in hdac_detach()
1764 for (i = 0; i < sc->num_ss; i++) in hdac_detach()
1765 hdac_dma_free(sc, &sc->streams[i].bdl); in hdac_detach()
1766 free(sc->streams, M_HDAC); in hdac_detach()
1767 hdac_dma_free(sc, &sc->pos_dma); in hdac_detach()
1768 hdac_dma_free(sc, &sc->rirb_dma); in hdac_detach()
1769 hdac_dma_free(sc, &sc->corb_dma); in hdac_detach()
1770 if (sc->chan_dmat != NULL) { in hdac_detach()
1771 bus_dma_tag_destroy(sc->chan_dmat); in hdac_detach()
1772 sc->chan_dmat = NULL; in hdac_detach()
1775 snd_mtxfree(sc->lock); in hdac_detach()
1784 return (sc->chan_dmat); in hdac_get_dma_tag()
1815 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, in hdac_child_pnpinfo_method()
1816 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); in hdac_child_pnpinfo_method()
1831 *result = sc->codecs[cad].vendor_id; in hdac_read_ivar()
1834 *result = sc->codecs[cad].device_id; in hdac_read_ivar()
1837 *result = sc->codecs[cad].revision_id; in hdac_read_ivar()
1840 *result = sc->codecs[cad].stepping_id; in hdac_read_ivar()
1849 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; in hdac_read_ivar()
1852 *result = (1 << (1 << sc->num_sdo)) - 1; in hdac_read_ivar()
1865 return (sc->lock); in hdac_get_mtx()
1881 ss = -1; in hdac_find_stream()
1884 for (i = 0; i < sc->num_iss; i++) { in hdac_find_stream()
1885 if (sc->streams[i].stream == stream) { in hdac_find_stream()
1891 for (i = 0; i < sc->num_oss; i++) { in hdac_find_stream()
1892 if (sc->streams[i + sc->num_iss].stream == stream) { in hdac_find_stream()
1893 ss = i + sc->num_iss; in hdac_find_stream()
1899 if (ss == -1) { in hdac_find_stream()
1900 for (i = 0; i < sc->num_bss; i++) { in hdac_find_stream()
1901 if (sc->streams[i + sc->num_iss + sc->num_oss].stream in hdac_find_stream()
1903 ss = i + sc->num_iss + sc->num_oss; in hdac_find_stream()
1929 bw *= 1 << (sc->num_sdo - stripe); in hdac_stream_alloc()
1930 prevbw = sc->sdo_bw_used; in hdac_stream_alloc()
1931 maxbw = 48000 * 960 * (1 << sc->num_sdo); in hdac_stream_alloc()
1933 prevbw = sc->codecs[cad].sdi_bw_used; in hdac_stream_alloc()
1939 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); in hdac_stream_alloc()
1944 sc->sdo_bw_used += bw; in hdac_stream_alloc()
1946 sc->codecs[cad].sdi_bw_used += bw; in hdac_stream_alloc()
1949 if (ss >= sc->num_iss + sc->num_oss) in hdac_stream_alloc()
1950 stream = 15 - (ss - sc->num_iss - sc->num_oss); in hdac_stream_alloc()
1951 else if (ss >= sc->num_iss) in hdac_stream_alloc()
1952 stream = ss - sc->num_iss + 1; in hdac_stream_alloc()
1956 sc->streams[ss].dev = child; in hdac_stream_alloc()
1957 sc->streams[ss].dir = dir; in hdac_stream_alloc()
1958 sc->streams[ss].stream = stream; in hdac_stream_alloc()
1959 sc->streams[ss].bw = bw; in hdac_stream_alloc()
1960 sc->streams[ss].format = format; in hdac_stream_alloc()
1961 sc->streams[ss].stripe = stripe; in hdac_stream_alloc()
1963 if (sc->pos_dma.dma_vaddr != NULL) in hdac_stream_alloc()
1964 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); in hdac_stream_alloc()
1982 sc->sdo_bw_used -= sc->streams[ss].bw; in hdac_stream_free()
1984 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; in hdac_stream_free()
1985 sc->streams[ss].stream = 0; in hdac_stream_free()
1986 sc->streams[ss].dev = NULL; in hdac_stream_free()
2004 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; in hdac_stream_start()
2006 bdle->addrl = htole32((uint32_t)addr); in hdac_stream_start()
2007 bdle->addrh = htole32((uint32_t)(addr >> 32)); in hdac_stream_start()
2008 bdle->len = htole32(blksz); in hdac_stream_start()
2009 bdle->ioc = htole32(1); in hdac_stream_start()
2013 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag, in hdac_stream_start()
2014 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_PREWRITE); in hdac_stream_start()
2017 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); in hdac_stream_start()
2018 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); in hdac_stream_start()
2019 addr = sc->streams[ss].bdl.dma_paddr; in hdac_stream_start()
2020 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); in hdac_stream_start()
2021 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); in hdac_stream_start()
2023 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); in hdac_stream_start()
2031 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; in hdac_stream_start()
2032 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); in hdac_stream_start()
2034 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); in hdac_stream_start()
2036 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); in hdac_stream_start()
2038 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); in hdac_stream_start()
2040 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, in hdac_stream_start()
2042 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); in hdac_stream_start()
2045 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); in hdac_stream_start()
2047 sc->streams[ss].blksz = blksz; in hdac_stream_start()
2048 sc->streams[ss].running = 1; in hdac_stream_start()
2064 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag, in hdac_stream_stop()
2065 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_POSTWRITE); in hdac_stream_stop()
2068 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); in hdac_stream_stop()
2071 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); in hdac_stream_stop()
2073 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); in hdac_stream_stop()
2075 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); in hdac_stream_stop()
2077 sc->streams[ss].running = 0; in hdac_stream_stop()
2095 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); in hdac_stream_reset()
2097 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); in hdac_stream_reset()
2099 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); in hdac_stream_reset()
2103 } while (--to); in hdac_stream_reset()
2107 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); in hdac_stream_reset()
2110 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); in hdac_stream_reset()
2114 } while (--to); in hdac_stream_reset()
2130 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); in hdac_stream_getptr()
2138 sc->unsol_registered++; in hdac_unsol_alloc()
2148 sc->unsol_registered--; in hdac_unsol_free()